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An ergonomic, featureful, and easy-to-integrate implementation of the GDB Remote Serial Protocol in Rust (with no-compromises #![no_std] support)

Rust 318 51 Updated Jan 5, 2025

Simple, single-file, dependency-free GDB stub that can be easily dropped in to your project.

C 220 24 Updated Oct 7, 2022

A new markup-based typesetting system that is powerful and easy to learn.

Rust 36,777 992 Updated Jan 16, 2025

The RISC-V External Debug Security Specification

Makefile 19 4 Updated Jan 14, 2025

Xv6 for RISC-V

C 7,479 2,740 Updated Sep 6, 2024

RISC-V Nexus Trace TG documentation and reference code

C 48 35 Updated Jan 3, 2025

Instruction Set Generator initially contributed by Futurewei

C++ 271 61 Updated Oct 17, 2023

Trace Decoder for SiFive's Freedom Platform

Makefile 1 3 Updated Mar 18, 2021

RISC-V Debug Support for our PULP RISC-V Cores

SystemVerilog 236 78 Updated Nov 11, 2024

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

SystemVerilog 999 430 Updated Jul 19, 2024

Scripts for XiangShan

Verilog 13 14 Updated Jan 14, 2025

程序员在家做饭方法指南。Programmer's guide about how to cook at home (Simplified Chinese only).

Dockerfile 68,657 8,803 Updated Jan 18, 2025

SoftFloat release 3

C 252 141 Updated Aug 4, 2024
C 3 Updated Dec 28, 2023

This repo includes XiangShan's function units

Scala 18 12 Updated Jan 17, 2025

synthesiseable ieee 754 floating point library in verilog

Verilog 550 148 Updated Mar 13, 2023

HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve

Verilog 88 25 Updated Oct 31, 2023

Simplified Chinese translation extension for AUTOMATIC1111's stable diffusion webui

1,527 160 Updated Sep 16, 2024

🔧 .files, including ~/.macos — sensible hacker defaults for macOS

Shell 30,495 8,728 Updated Aug 5, 2024

ShellCheck, a static analysis tool for shell scripts

Haskell 36,787 1,790 Updated Dec 14, 2024

RISC-V CPU Core (RV32IM)

Verilog 1,329 243 Updated Sep 18, 2021

LuCI - OpenWrt Configuration Interface

JavaScript 6,557 2,588 Updated Jan 17, 2025

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

SystemVerilog 1,442 563 Updated Jan 16, 2025

A generic test bench written in Bluespec

Bluespec 47 14 Updated Dec 15, 2020
Scala 1 1 Updated Jan 3, 2023

Scala Circuit IR Tools

Scala 6 Updated Jun 29, 2022

DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language

Scala 83 11 Updated Jan 12, 2025
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