Fixes for Xilinx Zynq UltraScale+ MPSoC#499

Merged

danielinux merged 5 commits intowolfSSL:masterfrom dgarske:zynqmp_makegcc

Dec 30, 2024

+2,298-930

Commits on Dec 10, 2024

Fixes for Xilinx Zynq UltraScale+ MPSoC:
dgarske
committed

Commits on Dec 14, 2024

Added QSPI DMA support.
dgarske
committed

Commits on Dec 19, 2024

Fixes for QSPI DMA mode. For example reduces QSPI->DDR load of 154MB from 18,228ms to 2,607ms. Changed QSPI to use DMA by default (can force IO mode using GQSPI_MODE_IO).
dgarske
committed

Commits on Dec 20, 2024

Make flush_dcache_range available even with USE_BUILTIN_STARTUP. Remove unused variable.
dgarske
committed

Commits on Dec 26, 2024

Allow build-time adjustment of QSPI reference clock and divisor. Eliminate ZCU102 macro (not needed). Add QSPI init message with ref clock, divisor, bus and IO mode (Poll or DMA).
dgarske
committed