Updated lecture 2

wulffern · Dec 7, 2023 · 23d4098 · 23d4098
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diff --git a/Makefile b/Makefile
@@ -8,8 +8,8 @@ FILES = lectures/l00_diode \
 	lectures/l00_refresher \
 	lectures/lp_project_report \
 	lectures/l01_intro \
-#	lectures/l02_esd \
-	lectures/l03_refbias \
+	lectures/l02_esd \
+#	lectures/l03_refbias \
 	lectures/l04_afe \
 	lectures/l05_sc \
 	lectures/l06_adc \

diff --git a/docs/plan.md b/docs/plan.md
@@ -5,22 +5,23 @@ permalink: /plan/
 ---
 
 
-| Week | Book                 | Thursday                  | Topics                                                      |
-|------|----------------------|---------------------------|-------------------------------------------------------------|
-| 2    | CJM 1-6              | Introduction              | Info, Refresh                                               |
-| 3    |                      | ICs and their components  | Refresh, IC components, ESD, GGNMOS, Latchup                |
-| 4    | CJM 7,8              | Reference and bias        | Diode voltage, bandgaps, low voltage bandgaps, bias sources |
-| 5    | CJM 12               | Filters and DACs          | Filter synthesis, Gm-C, Active-RC, DACs                     |
-| 6    | CJM 11-14            | Switched capacitor        | Discrete-Time, Z-domain, Switched capacitor                 |
-| 7    | CJM 18               | Oversampling converters   | FOM, Quantization, Oversampling, Noise shaping, Sigma-Delta |
-| 8    |                      | Winter holiday            |                                                             |
-| 9    | CJM 7.4, CFAS,+DC/DC | Voltage regulation        | LDO, ULP, BUCK, BOOST, PWM, PFM                             |
-| 10   | CJM 19, CFAS         | PLLs                      | Calculation, VCO, PFD, Loop-filter, dividers                |
-| 11   | Paper                | Oscillators               | RC-Oscillators, Crystal oscillators                         |
-| 12   | Slides               | Low-power radio receivers | GFSK, QPSK, PSK, QAM, radio blocks                          |
-| 13   |                      | Easter                    |                                                             |
-| 14   |                      | Easter                    |                                                             |
-| 15   |                      | Analog SystemVerilog      | analog system verilog behavioral models and energy sources  |
-| 16   |                      | Q & A                     |                                                             |
-| 17   |                      | Q & A                     |                                                             |
+| Week | Book                 | Project | Lecture                   | Topics                                                      |
+|------|----------------------|---------|---------------------------|-------------------------------------------------------------|
+| 2    | CJM 1-6              |         | Introduction              | Info, Refresh                                               |
+| 3    |                      |         | ICs and their components  | Refresh, IC components, ESD, GGNMOS, Latchup                |
+| 4    | CJM 7,8              |         | Reference and bias        | Diode voltage, bandgaps, low voltage bandgaps, bias sources |
+| 5    | CJM 12               |         | Filters and DACs          | Filter synthesis, Gm-C, Active-RC, DACs                     |
+| 6    | CJM 11-14            | M1      | Switched capacitor        | Discrete-Time, Z-domain, Switched capacitor                 |
+| 7    | CJM 18               |         | Oversampling converters   | FOM, Quantization, Oversampling, Noise shaping, Sigma-Delta |
+| 8    |                      |         | Winter holiday            |                                                             |
+| 9    | CJM 7.4, CFAS,+DC/DC | M2      | Voltage regulation        | LDO, ULP, BUCK, BOOST, PWM, PFM                             |
+| 10   | CJM 19, CFAS         |         | PLLs                      | Calculation, VCO, PFD, Loop-filter, dividers                |
+| 11   | Paper                |         | Oscillators               | RC-Oscillators, Crystal oscillators                         |
+| 12   | Slides               | M3      | Low-power radio receivers | GFSK, QPSK, PSK, QAM, radio blocks                          |
+| 13   |                      |         | Easter                    |                                                             |
+| 14   |                      |         | Easter                    |                                                             |
+| 15   |                      | M4      | Analog SystemVerilog      | analog system verilog behavioral models and energy sources  |
+| 16   |                      |         | Q & A                     |                                                             |
+| 17   |                      |         | Q & A                     |                                                             |
+| 18   |                      | M5      | Q & A                     |                                                             |
 
diff --git a/dot/Makefile b/dot/Makefile
@@ -2,3 +2,4 @@
 
 figs:
 	cat dig_des.dot | dot -Tsvg  > ../media/dig_des.svg
+	cat dig_des_lr.dot | dot -Tsvg  > ../media/dig_des_lr.svg
diff --git a/lectures/l01_intro.md b/lectures/l01_intro.md
@@ -117,11 +117,15 @@ If you like the world to be ordered, with definite answers, then it's likely tha
 If you're comfortable with not knowing, and an insatiable desire to understand how the world *really* works at a fundamental level, then 
 it's likely that you'll find analog flow interesting. 
 
+![inline](../media/dig_des.svg)
+
 -->
 
 ---
 
-![inline](../media/dig_des.svg)
+<!--pan_skip: -->
+
+![inline](../media/dig_des_lr.svg)
 
 ---
 
@@ -274,13 +278,14 @@ my understanding is wrong, then I'll happily discuss.
 **Lectures:**
 Friday at 08:15 - 10:00
 
-The "lectures" will be Q & A's on the topic. If no questions, then I'll ramble on
+Read the introduction before the lectures at [aic2024](https://analogicus.com/aic2024)
 
-**Exercise Hours:**
-Friday at 10:15 - 12:00
+The "lectures" will be Q & A's on the topic. If no questions, then I'll ramble on.
 
-The TA will be in the "exercise hours", and I also will hopefully join most days.
+**Project Hours:**
+Friday at 10:15 - 12:00
 
+The TA will be in the "project hours", and I will join most days.
 
 ---
 
@@ -290,7 +295,7 @@ The TA will be in the "exercise hours", and I also will hopefully join most days
 
 - [Description](https://www.ntnu.no/studier/emner/TFE4188#tab=omEmnet)
 
-- [Time schedule](https://tp.uio.no/ntnu/timeplan/?id=TFE4188&sem=24v&sort=form&type=course)
+- [Time schedule](https://www.ntnu.no/studier/emner/TFE4188#tab=timeplan)
 
 - [Lecture plan](https://wulffern.github.io/aic2024/plan/)
 
@@ -314,7 +319,7 @@ Buy a hard-copy of the book if you don't have that. Don't expect to understand t
 
 -->
 
-![inline](../media/cjm.png) ![inline](../media/cfas.png)
+![inline](../media/cjm.png)
 
 
 ---
@@ -323,9 +328,10 @@ Buy a hard-copy of the book if you don't have that. Don't expect to understand t
 
 ## Exam
 
-- May/June 2022?
+- June 2022
 - 4 hours
 - A - F grade (F = Fail)
+- Counts for 55 % of the grade
 
 ---
 <!--pan_skip: -->
@@ -344,7 +350,7 @@ Buy a hard-copy of the book if you don't have that. Don't expect to understand t
 - For the rest, two options:
   - Don't do the exercises, don't get feedback
   - Do the exercises, hand them in within deadline, get feedback
-- The TA's will only support the exercises in the marked weeks
+- The TA will only support the exercises in the marked weeks
 
 ---
 
@@ -411,7 +417,6 @@ The fourth milestone is the report, while the fifth milestone is the layout.
 
 ---
 
-
 ![fit](../media/project_plan.pdf)
 
 
@@ -437,18 +442,28 @@ During the first group session of a milestone, you will
 
 **Check-in (10 minutes)**
 
-Each member of the group says how they feel. Some examples could be:
+Some example questions could be 
+
+- Share one thing that is going on in your life (personal or professional.)
+- What is one thing that you are grateful for right now?
+- What is something funny that happened?
+
+Some examples answers could be:
 - My dog died yesterday, so I'm not feeling great today.
-- I woke up early, had an omelette, and went running, so I feel motivated and fantastic.
+- I woke up early, had an omelet, and went running, so I feel motivated and fantastic.
 - I feel *blaaah* today, motivation is lacking. 
+- I went running yesterday and did not discover before I got home that I'd forgotten to put my pants on, even though it was
+  -10 C.
 
-The point of this excersize is to get to know eachother a bit, and attempt to create pshycological safety in the group.
+The point of this exercise is to get to know each other a bit, and attempt to create psychological safety in the group.
 
-**Ideas (30 minutes)**
+**Ideas (35 minutes)**
 
 Come up with ideas for how the milestone could be implemented. What circuit ideas could work? 
 
-**Plan (10 minutes)**
+**Break (15 minutes)**
+
+**Plan (20 minutes)**
 
 Sketch out who does what the next week. What's the goal for the week. 
 
@@ -467,11 +482,11 @@ Each group member talks about their one word.
 You shall always Check-in, Reflect and Discuss. Although some may consider it a waste of time, it's important to improve the
 group dynamics.
 
-**Review (30 minutes)**
+**Review (35 minutes)**
 
 Go through the plan from last week, what worked, what did not work, what should be done differently.  Discuss.
 
-**Plan (10 minutes)**
+**Plan (20 minutes)**
 
 Sketch out who does what the next week. What's the goal for the week. 
 
@@ -500,7 +515,7 @@ I've made a rather detailed (at least I think so myself) tutorial on how to make
 I strongly recommend you start with that first. 
 -->
 
- [rply\_ex0\_sky130nm](https://wulffern.github.io/rply_ex0_sky130nm)
+ [Skywater 130 nm Tutorial](https://analogicus.com/aic2024/2023/11/16/Tools.html)
 
 
 <!--pan_doc:

diff --git a/lectures/l02_esd.md b/lectures/l02_esd.md
@@ -4,7 +4,7 @@ autoscale:true
 theme: Plain Jane, 1
 text:  Helvetica
 header:  Helvetica
-
+date: 2024-01-19
 
 <!--pan_title: Lecture 2 - IC and ESD  -->
 
@@ -16,7 +16,7 @@ header:  Helvetica
 
 <!--pan_skip: -->
 
-## [TFE4188 - Introduction to Lecture 2](https://wulffern.github.io/aic2023/2023/01/19/Lecture-2-IC-and-ESD.html)
+## TFE4188 - Introduction to Lecture 2
 # ICs and ESD
 
 ---
@@ -31,13 +31,6 @@ Understand why you must **always handle ESD** on an IC
 
 ---
 
-<!--pan_skip: -->
-
-#[fit] RPLY
-
-The project for 2023 is to design an integrated temperature sensor. The hope is that some will tapeout on the Google/Efabless Open MPW shuttle
-
----
 
 <!--pan_skip: -->
 
@@ -50,7 +43,7 @@ The project for 2023 is to design an integrated temperature sensor. The hope is
 <!--pan_doc:
 
 
-The project for 2023 is to design an integrated temperature sensor. The hope is that some will tapeout on the Google/Efabless Open MPW shuttle
+The project for 2024 is to design an integrated temperature sensor. 
 
 First, we need to have an idea of what comes in and out of the temperature
 sensor. Before we have made the temperature sensor, we need to think what the signal interface could be, and we need to learn.
@@ -83,6 +76,7 @@ We're using Skywater, and to use the free tapeouts we must use the [Caravel](htt
 test chip harness.
 
 That luckily has two supplies. It can be powered externally by up to 5.0 V, and has an external low dropout regulator (LDO) that provides the digital supply (1.8 V).
+
 See more at [Absolute maximum ratings](https://caravel-harness.readthedocs.io/en/latest/maximum-ratings.html)
 
 ### Ground 
@@ -108,7 +102,7 @@ Even a temperature sensor needs something else on the IC. We need digital input/
 
 I would claim that any System-On-Chip will always need these blocks!
 
-I want you to pause, take a look at the [course plan](https://wulffern.github.io/aic2023/plan/), and now you might understand why I've selected the topics.
+I want you to pause, take a look at the [course plan](https://wulffern.github.io/aic2024/plan/), and now you might understand why I've selected the topics.
 
 ### One more thing
 There is one more function we need when we have digital logic and a power supply. We need a "RESET" system. 
@@ -123,7 +117,6 @@ How would we know?
 Most ICs will have a special analog block that can keep the digital logic, bias generators, clock generators, input/output and voltage regulators in a **safe**
 state until the power supply is high enough (for example 1.62 V). 
 
-
 -->
 
 
@@ -141,12 +134,14 @@ If you make an IC, you must consider Electrostatic Discharge (ESD) Protection ci
 <!--pan_doc: 
 
 ESD events are tricky. They are short (ns), high current (Amps) and poorly modeled in the SPICE model. 
+
 Most SPICE models will not model correctly what happens to an transistor during an ESD event. The SPICE models are not made to
 model what happens during an ESD event, they are made to model how the transistors behave at low fields and lower current.
 
 But ESD design is a must, you have to think about ESD, otherwise your IC will never work. 
 
 Consider a certain ESD specification, for example 1 kV human body model, a requirement for an integrated circuit. 
+
 By requirement I mean if the 1 kV is not met, then the project will be delayed until it is fixed. If it's not fixed, then the
 project will be infinitely delayed, or in other words, canceled.
 
@@ -181,6 +176,7 @@ Standards for testing at [JEDEC](https://www.jedec.org/category/technology-focus
 <!--pan_doc: 
 
 Models a person touching a device with a finger.
+
 -->
 
 **Charged device model (CDM)**
@@ -333,7 +329,7 @@ We want a circuit that most of the time sleeps, and does not affect our normal I
 a huge current comes in on VDD, and the VDD voltage shoots up fast, the circuit must wake up and bring the voltage down.
 
 If the circuit triggers under normal operating condition, when your watching a video on your phone, your battery will 
-drain very fast, and it might even catch fire.
+drain very fast, and your phone might even catch fire.
 
 As such, ESD design engineers have a "ESD design window". Never let the ESD circuit trigger when VDD < normal, but always trigger the ESD circuit 
 before VDD $>$ breakdown of circuit.
@@ -381,7 +377,7 @@ when they scatter off an atom. If you break too many bonds between atoms, your m
 
 Assume a transistor like the one below. The gate, source and bulk is connected to ground. The drain is connected to a high voltage.
 
-![](../media/physics/ggnmos.pdf)
+![](../media/ggnmos.pdf)
 
 
 ### Avalanche 
@@ -472,7 +468,7 @@ Assume we have the circuit below.
 
 We can draw a cross section of the inverter.
 
-![](../media/physics/scr_eh.pdf)
+![](../media/scr_eh.pdf)
 
 ### Electron injection