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disable trace in CI
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gadfort committed Jul 9, 2024
1 parent 3099370 commit 24c385d
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Showing 12 changed files with 13 additions and 13 deletions.
4 changes: 2 additions & 2 deletions umi/lumi/testbench/test_lumi.py
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Expand Up @@ -13,7 +13,7 @@


def build_testbench(topo="2d", trace=False):
dut = SbDut('testbench', trace=True, trace_type='fst', default_main=True)
dut = SbDut('testbench', trace=False, trace_type='fst', default_main=True)

# Set up inputs
dut.input('lumi/testbench/testbench_lumi.sv', package='umi')
Expand All @@ -39,7 +39,7 @@ def build_testbench(topo="2d", trace=False):
dut.add('tool', 'verilator', 'task', 'compile', 'option', '-Wall')

# Settings - enable tracing
dut.set('option', 'trace', True)
dut.set('option', 'trace', False)
dut.set('tool', 'verilator', 'task', 'compile', 'var', 'trace_type', 'fst')

# Build simulator
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2 changes: 1 addition & 1 deletion umi/lumi/testbench/test_lumi_rnd.py
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@


def build_testbench(topo="2d", trace=False):
dut = SbDut('testbench', trace=True, trace_type='fst', default_main=True)
dut = SbDut('testbench', trace=False, trace_type='fst', default_main=True)

# Set up inputs
dut.input('lumi/testbench/testbench_lumi.sv', package='umi')
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2 changes: 1 addition & 1 deletion umi/umi/testbench/test_crossbar.py
Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,7 @@ def build_testbench():
dut.add('tool', 'verilator', 'task', 'compile', 'option', '-Wall')

# Settings - enable tracing
dut.set('option', 'trace', True)
dut.set('option', 'trace', False)
dut.set('tool', 'verilator', 'task', 'compile', 'var', 'trace_type', 'fst')

# Build simulator
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2 changes: 1 addition & 1 deletion umi/umi/testbench/test_fifo.py
Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ def build_testbench():
dut.add('tool', 'verilator', 'task', 'compile', 'option', '-Wall')

# Settings - enable tracing
dut.set('option', 'trace', True)
dut.set('option', 'trace', False)
dut.set('tool', 'verilator', 'task', 'compile', 'var', 'trace_type', 'fst')

# Build simulator
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2 changes: 1 addition & 1 deletion umi/umi/testbench/test_fifo_flex.py
Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,7 @@ def build_testbench(split=False):
dut.add('tool', 'verilator', 'task', 'compile', 'option', '-Wall')

# Settings - enable tracing
dut.set('option', 'trace', True)
dut.set('option', 'trace', False)
dut.set('tool', 'verilator', 'task', 'compile', 'var', 'trace_type', 'fst')

# Build simulator
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2 changes: 1 addition & 1 deletion umi/umi/testbench/test_mem_agent.py
Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@ def build_testbench():
dut.add('tool', 'verilator', 'task', 'compile', 'option', '-Wall')

# Settings - enable tracing
dut.set('option', 'trace', True)
dut.set('option', 'trace', False)
dut.set('tool', 'verilator', 'task', 'compile', 'var', 'trace_type', 'fst')

# Build simulator
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2 changes: 1 addition & 1 deletion umi/umi/testbench/test_regif.py
Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@ def build_testbench():
dut.add('tool', 'verilator', 'task', 'compile', 'option', '-Wall')

# Settings - enable tracing
dut.set('option', 'trace', True)
dut.set('option', 'trace', False)
dut.set('tool', 'verilator', 'task', 'compile', 'var', 'trace_type', 'fst')

# Build simulator
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2 changes: 1 addition & 1 deletion umi/umi/testbench/test_umi_ram.py
Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ def build_testbench():
dut.add('tool', 'verilator', 'task', 'compile', 'option', '-Wall')

# Settings - enable tracing
dut.set('option', 'trace', True)
dut.set('option', 'trace', False)
dut.set('tool', 'verilator', 'task', 'compile', 'var', 'trace_type', 'fst')

# Build simulator
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2 changes: 1 addition & 1 deletion umi/utils/testbench/test_umi2axilite.py
Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@ def build_testbench():
dut.add('tool', 'verilator', 'task', 'compile', 'option', '-Wall')

# Settings - enable tracing
dut.set('option', 'trace', True)
dut.set('option', 'trace', False)
dut.set('tool', 'verilator', 'task', 'compile', 'var', 'trace_type', 'fst')

# Build simulator
Expand Down
2 changes: 1 addition & 1 deletion umi/utils/testbench/test_umi2tl_np.py
Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,7 @@ def build_testbench(topo="2d"):
dut.add('tool', 'verilator', 'task', 'compile', 'option', '-Wall')

# Settings - enable tracing
dut.set('option', 'trace', True)
dut.set('option', 'trace', False)
dut.set('tool', 'verilator', 'task', 'compile', 'var', 'trace_type', 'fst')

# Build simulator
Expand Down
2 changes: 1 addition & 1 deletion umi/utils/testbench/test_umi_address_remap.py
Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ def build_testbench(topo="2d"):
dut.add('tool', 'verilator', 'task', 'compile', 'option', '-Wall')

# Settings - enable tracing
dut.set('option', 'trace', True)
dut.set('option', 'trace', False)
dut.set('tool', 'verilator', 'task', 'compile', 'var', 'trace_type', 'fst')

# Build simulator
Expand Down
2 changes: 1 addition & 1 deletion umi/utils/testbench/test_umi_packet_merge_greedy.py
Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,7 @@ def build_testbench(topo="2d"):
dut.add('tool', 'verilator', 'task', 'compile', 'option', '-Wall')

# Settings - enable tracing
dut.set('option', 'trace', True)
dut.set('option', 'trace', False)
dut.set('tool', 'verilator', 'task', 'compile', 'var', 'trace_type', 'fst')

# Build simulator
Expand Down

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