Merge pull request #178 from zeroasiccorp/ali/lumi

LUMI rtl and test changes
zeroasiccorp · Oct 2, 2024 · 63bb3e6 · 63bb3e6
2 parents 819a19c + 9ad1768
commit 63bb3e6
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diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
@@ -23,7 +23,7 @@ jobs:
           . venv/bin/activate
           python3 -m pip install --upgrade pip
           python3 -m pip install -e .[test]
-          pytest -m "switchboard" -n auto
+          pytest -m "switchboard"
 
   python_ci:
     name: "Python + Tools CI"

diff --git a/pyproject.toml b/pyproject.toml
@@ -53,6 +53,7 @@ markers = [
 ]
 testpaths = [
     "tests",
-    "umi/sumi/tests"
+    "umi/sumi/tests",
+    "umi/lumi/tests"
 ]
 timeout = "300"
diff --git a/umi/conftest.py b/umi/conftest.py
@@ -0,0 +1,39 @@
+import pytest
+import os
+import multiprocessing
+
+
+@pytest.fixture(autouse=True)
+def test_wrapper(tmp_path):
+    '''
+    Fixture that automatically runs each test in a test-specific temporary
+    directory to avoid clutter.
+    '''
+    try:
+        multiprocessing.set_start_method('fork')
+    except RuntimeError:
+        pass
+
+    topdir = os.getcwd()
+    os.chdir(tmp_path)
+
+    # Run the test.
+    yield
+
+    os.chdir(topdir)
+
+
+def pytest_addoption(parser):
+    parser.addoption("--seed", type=int, action="store", help="Provide a fixed seed")
+
+
+@pytest.fixture
+def random_seed(request):
+    fixed_seed = request.config.getoption("--seed")
+    if fixed_seed is not None:
+        test_seed = fixed_seed
+    else:
+        test_seed = os.getpid()
+    print(f'Random seed used: {test_seed}')
+    yield test_seed
+    print(f'Random seed used: {test_seed}')
diff --git a/umi/lumi/rtl/lumi.v b/umi/lumi/rtl/lumi.v
@@ -141,7 +141,10 @@ module lumi
    wire [7:0]           csr_rxiowidth;
    wire                 csr_txcrdt_en;
    wire [15:0]          csr_txcrdt_intrvl;
-   wire [31:0]          csr_txcrdt_status;
+   wire [31:0]          csr_req_txcrdt_navail;
+   wire [31:0]          csr_resp_txcrdt_navail;
+   wire [31:0]          csr_req_txcrdt_avail;
+   wire [31:0]          csr_resp_txcrdt_avail;
    wire                 csr_txen;
    wire [7:0]           csr_txiowidth;
    wire [CW-1:0]        fifo2cb_cmd;
@@ -193,36 +196,39 @@ module lumi
                )
    lumi_regs(/*AUTOINST*/
              // Outputs
-             .udev_req_ready    (cb2regs_ready),         // Templated
-             .udev_resp_valid   (regs2cb_valid),         // Templated
-             .udev_resp_cmd     (regs2cb_cmd[CW-1:0]),   // Templated
-             .udev_resp_dstaddr (regs2cb_dstaddr[AW-1:0]), // Templated
-             .udev_resp_srcaddr (regs2cb_srcaddr[AW-1:0]), // Templated
-             .udev_resp_data    (regs2cb_data[RW-1:0]),  // Templated
-             .host_linkactive   (host_linkactive),
-             .csr_arbmode       (),                      // Templated
-             .csr_txen          (csr_txen),
-             .csr_txcrdt_en     (csr_txcrdt_en),
-             .csr_txiowidth     (csr_txiowidth[7:0]),
-             .csr_rxen          (csr_rxen),
-             .csr_rxiowidth     (csr_rxiowidth[7:0]),
-             .csr_txcrdt_intrvl (csr_txcrdt_intrvl[15:0]),
-             .csr_rxcrdt_req_init(csr_rxcrdt_req_init[15:0]),
-             .csr_rxcrdt_resp_init(csr_rxcrdt_resp_init[15:0]),
+             .udev_req_ready            (cb2regs_ready),         // Templated
+             .udev_resp_valid           (regs2cb_valid),         // Templated
+             .udev_resp_cmd             (regs2cb_cmd[CW-1:0]),   // Templated
+             .udev_resp_dstaddr         (regs2cb_dstaddr[AW-1:0]), // Templated
+             .udev_resp_srcaddr         (regs2cb_srcaddr[AW-1:0]), // Templated
+             .udev_resp_data            (regs2cb_data[RW-1:0]),  // Templated
+             .host_linkactive           (host_linkactive),
+             .csr_arbmode               (),                      // Templated
+             .csr_txen                  (csr_txen),
+             .csr_txcrdt_en             (csr_txcrdt_en),
+             .csr_txiowidth             (csr_txiowidth[7:0]),
+             .csr_rxen                  (csr_rxen),
+             .csr_rxiowidth             (csr_rxiowidth[7:0]),
+             .csr_txcrdt_intrvl         (csr_txcrdt_intrvl[15:0]),
+             .csr_rxcrdt_req_init       (csr_rxcrdt_req_init[15:0]),
+             .csr_rxcrdt_resp_init      (csr_rxcrdt_resp_init[15:0]),
              // Inputs
-             .devicemode        (devicemode),
-             .deviceready       (deviceready),
-             .nreset            (nreset),
-             .clk               (clk),
-             .udev_req_valid    (cb2regs_valid),         // Templated
-             .udev_req_cmd      (cb2regs_cmd[CW-1:0]),   // Templated
-             .udev_req_dstaddr  (cb2regs_dstaddr[AW-1:0]), // Templated
-             .udev_req_srcaddr  (cb2regs_srcaddr[AW-1:0]), // Templated
-             .udev_req_data     (cb2regs_data[RW-1:0]),  // Templated
-             .udev_resp_ready   (regs2cb_ready),         // Templated
-             .phy_linkactive    (phy_linkactive),
-             .phy_iow           (phy_iow[7:0]),
-             .csr_txcrdt_status (csr_txcrdt_status[31:0]));
+             .devicemode                (devicemode),
+             .deviceready               (deviceready),
+             .nreset                    (nreset),
+             .clk                       (clk),
+             .udev_req_valid            (cb2regs_valid),         // Templated
+             .udev_req_cmd              (cb2regs_cmd[CW-1:0]),   // Templated
+             .udev_req_dstaddr          (cb2regs_dstaddr[AW-1:0]), // Templated
+             .udev_req_srcaddr          (cb2regs_srcaddr[AW-1:0]), // Templated
+             .udev_req_data             (cb2regs_data[RW-1:0]),  // Templated
+             .udev_resp_ready           (regs2cb_ready),         // Templated
+             .phy_linkactive            (phy_linkactive),
+             .phy_iow                   (phy_iow[7:0]),
+             .csr_req_txcrdt_navail     (csr_req_txcrdt_navail),
+             .csr_resp_txcrdt_navail    (csr_resp_txcrdt_navail),
+             .csr_req_txcrdt_avail      (csr_req_txcrdt_avail),
+             .csr_resp_txcrdt_avail     (csr_resp_txcrdt_avail));
 
    //###########################
    // Register Crossbar
@@ -466,7 +472,10 @@ module lumi
            .umi_resp_in_ready   (uhost_resp_ready),      // Templated
            .phy_txdata          (phy_txdata[IOW-1:0]),
            .phy_txvld           (phy_txvld),
-           .csr_crdt_status     (csr_txcrdt_status[31:0]), // Templated
+           .csr_req_crdt_navail (csr_req_txcrdt_navail), // Templated
+           .csr_resp_crdt_navail(csr_resp_txcrdt_navail), // Templated
+           .csr_req_crdt_avail  (csr_req_txcrdt_avail), // Templated
+           .csr_resp_crdt_avail (csr_resp_txcrdt_avail), // Templated
            // Inputs
            .clk                 (clk),
            .nreset              (nreset),

diff --git a/umi/lumi/rtl/lumi_regmap.vh b/umi/lumi/rtl/lumi_regmap.vh
@@ -21,10 +21,13 @@
  ******************************************************************************/
 
 // registers (addr[7:0]), 32bit aligned
-localparam LUMI_CTRL        = 8'h00; // device configuration
-localparam LUMI_STATUS      = 8'h04; // device status
-localparam LUMI_TXMODE      = 8'h10; // tx operating mode
-localparam LUMI_RXMODE      = 8'h14; // rx operating mode
-localparam LUMI_CRDTINIT    = 8'h20; // Credit init value
-localparam LUMI_CRDTINTRVL  = 8'h24; // Credir update interval
-localparam LUMI_CRDTSTAT    = 8'h28; // Credit status
+localparam LUMI_CTRL           = 8'h00; // device configuration
+localparam LUMI_STATUS         = 8'h04; // device status
+localparam LUMI_TXMODE         = 8'h10; // tx operating mode
+localparam LUMI_RXMODE         = 8'h14; // rx operating mode
+localparam LUMI_CRDTINIT       = 8'h20; // Credit init value
+localparam LUMI_CRDTINTRVL     = 8'h24; // Credir update interval
+localparam LUMI_REQCRDTNAVAIL  = 8'h30; // Req credit not available
+localparam LUMI_RESPCRDTNAVAIL = 8'h34; // Resp credit not available
+localparam LUMI_REQCRDTAVAIL   = 8'h38; // Req credit available
+localparam LUMI_RESPCRDTAVAIL  = 8'h3C; // Resp credit available
diff --git a/umi/lumi/rtl/lumi_regs.v b/umi/lumi/rtl/lumi_regs.v
@@ -73,7 +73,11 @@ module lumi_regs
     output [15:0]   csr_txcrdt_intrvl,
     output [15:0]   csr_rxcrdt_req_init,
     output [15:0]   csr_rxcrdt_resp_init,
-    input [31:0]    csr_txcrdt_status
+    // performance counters
+    input [31:0]    csr_req_txcrdt_navail,
+    input [31:0]    csr_resp_txcrdt_navail,
+    input [31:0]    csr_req_txcrdt_avail,
+    input [31:0]    csr_resp_txcrdt_avail
     );
 
 `include "lumi_regmap.vh"
@@ -300,13 +304,16 @@ module lumi_regs
      else
        if (reg_read)
          case (reg_addr[7:2])
-           LUMI_CTRL[7:2]      : reg_rddata[RW-1:0] <= ctrl_reg[RW-1:0];
-           LUMI_STATUS[7:2]    : reg_rddata[RW-1:0] <= status_reg[RW-1:0];
-           LUMI_TXMODE[7:2]    : reg_rddata[RW-1:0] <= txmode_reg[RW-1:0];
-           LUMI_RXMODE[7:2]    : reg_rddata[RW-1:0] <= rxmode_reg[RW-1:0];
-           LUMI_CRDTINIT[7:2]  : reg_rddata[RW-1:0] <= {{RW-32{1'b0}},rxcrdt_init_reg[31:0]};
-           LUMI_CRDTINTRVL[7:2]: reg_rddata[RW-1:0] <= {{RW-16{1'b0}},txcrdt_intrvl_reg[15:0]};
-           LUMI_CRDTSTAT[7:2]  : reg_rddata[RW-1:0] <= {{RW-32{1'b0}},csr_txcrdt_status[31:0]};
+           LUMI_CTRL[7:2]          : reg_rddata[RW-1:0] <= ctrl_reg[RW-1:0];
+           LUMI_STATUS[7:2]        : reg_rddata[RW-1:0] <= status_reg[RW-1:0];
+           LUMI_TXMODE[7:2]        : reg_rddata[RW-1:0] <= txmode_reg[RW-1:0];
+           LUMI_RXMODE[7:2]        : reg_rddata[RW-1:0] <= rxmode_reg[RW-1:0];
+           LUMI_CRDTINIT[7:2]      : reg_rddata[RW-1:0] <= {{RW-32{1'b0}},rxcrdt_init_reg[31:0]};
+           LUMI_CRDTINTRVL[7:2]    : reg_rddata[RW-1:0] <= {{RW-16{1'b0}},txcrdt_intrvl_reg[15:0]};
+           LUMI_REQCRDTNAVAIL[7:2] : reg_rddata[RW-1:0] <= {{RW-32{1'b0}},csr_req_txcrdt_navail[31:0]};
+           LUMI_RESPCRDTNAVAIL[7:2]: reg_rddata[RW-1:0] <= {{RW-32{1'b0}},csr_resp_txcrdt_navail[31:0]};
+           LUMI_REQCRDTAVAIL[7:2]  : reg_rddata[RW-1:0] <= {{RW-32{1'b0}},csr_req_txcrdt_avail[31:0]};
+           LUMI_RESPCRDTAVAIL[7:2] : reg_rddata[RW-1:0] <= {{RW-32{1'b0}},csr_resp_txcrdt_avail[31:0]};
            default:
              reg_rddata[RW-1:0] <= 'b0;
          endcase

diff --git a/umi/lumi/rtl/lumi_tx.v b/umi/lumi/rtl/lumi_tx.v
@@ -56,7 +56,10 @@ module lumi_tx
     input             ioclk,
     input             ionreset,
     // Credit interface
-    output reg [31:0] csr_crdt_status,
+    output reg [31:0] csr_req_crdt_navail,
+    output reg [31:0] csr_resp_crdt_navail,
+    output reg [31:0] csr_req_crdt_avail,
+    output reg [31:0] csr_resp_crdt_avail,
     input [15:0]      csr_crdt_intrvl,
     input [15:0]      rmt_crdt_req,
     input [15:0]      rmt_crdt_resp,
@@ -202,16 +205,34 @@ module lumi_tx
           tx_crdt_req[15:0]  <= tx_crdt_req[15:0]  + {15'h0,shift_reg_type[0]};
        end
 
-   // Credit status - count cycles of no-credit
+   // Credit status - count cycles of credit/no-credit
 
    always @(posedge clk or negedge nreset)
      if (~nreset)
-       csr_crdt_status[31:0] <= 'h0;
+       csr_req_crdt_navail[31:0] <= 'b0;
      else
-       begin
-          csr_crdt_status[15:0]  <= csr_crdt_status[15:0]  + {15'h0000,(umi_req_in_valid   & phy_txrdy & ~rxready[0] & ~umi_resp_in_gated)};
-          csr_crdt_status[31:16] <= csr_crdt_status[31:16] + {15'h0000,(umi_resp_in_valid  & phy_txrdy & ~rxready[1])};
-       end
+       csr_req_crdt_navail[31:0] <= csr_req_crdt_navail[31:0] +
+                                    {31'h0, (umi_req_in_valid & phy_txrdy & ~rxready[0] &
+                                             ~umi_resp_in_gated)};
+
+   always @(posedge clk or negedge nreset)
+     if (~nreset)
+       csr_resp_crdt_navail[31:0] <= 'b0;
+     else
+       csr_resp_crdt_navail[31:0] <= csr_resp_crdt_navail[31:0] +
+                                     {31'h0, (umi_resp_in_valid & phy_txrdy & ~rxready[1])};
+
+   always @(posedge clk or negedge nreset)
+     if (~nreset)
+       csr_req_crdt_avail[31:0] <= 'b0;
+     else
+       csr_req_crdt_avail[31:0] <= csr_req_crdt_avail[31:0] + {31'h0, umi_req_in_ready};
+
+   always @(posedge clk or negedge nreset)
+     if (~nreset)
+       csr_resp_crdt_avail[31:0] <= 'b0;
+     else
+       csr_resp_crdt_avail[31:0] <= csr_resp_crdt_avail[31:0] + {31'h0, umi_resp_in_ready};
 
    //########################################
    //# Credit message generation for the remote side
@@ -245,19 +266,15 @@ module lumi_tx
    //# UMI Transmit Arbiter
    //########################################
 
-   // TODO: umi_mux should be changed as follows:
-   // .arbmode      (2'b00),
-   // .umi_in_valid ({umi_req_in_gated,umi_resp_in_gated}),
-
    // Mux together response and request over one data channel
    // the mux assumes one hot select (valid so need to prioritize the resp)
    /*umi_mux AUTO_TEMPLATE(
-    .arbmode           (2'b10),
+    .arbmode           (2'b00),
     .arbmask           ({2{1'b0}}),
     .umi_out_ready     (lumi_txrdy & ~(|crdt_updt_send)),
     .umi_out_valid     (),
     .umi_in_ready      ({umi_req_ready,umi_resp_ready}),
-    .umi_in_valid      ({umi_req_in_gated & ~umi_resp_in_gated,umi_resp_in_gated}),
+    .umi_in_valid      ({umi_req_in_gated,umi_resp_in_gated}),
     .umi_in_cmd        ({umi_req_in_cmd,umi_resp_in_cmd}),
     .umi_in_\(.*\)addr ({umi_req_in_\1addr,umi_resp_in_\1addr}),
     .umi_in_data       ({umi_req_in_data,umi_resp_in_data}),
@@ -278,9 +295,9 @@ module lumi_tx
            // Inputs
            .clk                 (clk),
            .nreset              (nreset),
-           .arbmode             (2'b10),
+           .arbmode             (2'b00),
            .arbmask             ({2{1'b0}}),
-           .umi_in_valid        ({umi_req_in_gated & ~umi_resp_in_gated,umi_resp_in_gated}), // Templated
+           .umi_in_valid        ({umi_req_in_gated,umi_resp_in_gated}), // Templated
            .umi_in_cmd          ({umi_req_in_cmd,umi_resp_in_cmd}), // Templated
            .umi_in_dstaddr      ({umi_req_in_dstaddr,umi_resp_in_dstaddr}), // Templated
            .umi_in_srcaddr      ({umi_req_in_srcaddr,umi_resp_in_srcaddr}), // Templated
@@ -421,9 +438,9 @@ module lumi_tx
    //# DATA SHIFT REGISTER
    //########################################
 
-   assign sample_packet = lumi_txrdy & csr_en & phy_txrdy & ((|crdt_updt_send) |
-                                                             umi_resp_in_gated |
-                                                             umi_req_in_gated  );
+   assign sample_packet = lumi_txrdy & phy_txrdy & ((|crdt_updt_send) |
+                                                    umi_resp_in_gated |
+                                                    umi_req_in_gated  );
 
    //########################################
    // UMI bandwidth optimization - send only what is needed
@@ -569,10 +586,10 @@ module lumi_tx
          end
      endcase
 
-   assign valid_start_value = lumi_txrdy & csr_en & (|crdt_updt_send) ?
-                              {{CW/8{1'b1}},{(DW+AW+AW)/8{1'b0}}}     :
-                              lumi_txrdy & umi_resp_in_gated          ?
-                              valid_start_value_resp                  :
+   assign valid_start_value = lumi_txrdy & (|crdt_updt_send)      ?
+                              {{CW/8{1'b1}},{(DW+AW+AW)/8{1'b0}}} :
+                              lumi_txrdy & umi_resp_in_gated      ?
+                              valid_start_value_resp              :
                               valid_start_value_req;
 
    // TX is done as lsb first

diff --git a/umi/lumi/tests/conftest.py b/umi/lumi/tests/conftest.py
@@ -0,0 +1,46 @@
+import pytest
+from switchboard import SbDut
+from umi import lumi
+from fasteners import InterProcessLock
+
+
+def pytest_collection_modifyitems(items):
+    for item in items:
+        if "lumi_dut" in getattr(item, "fixturenames", ()):
+            item.add_marker("switchboard")
+            pass
+
+
+@pytest.fixture
+def build_dir(pytestconfig):
+    return pytestconfig.cache.mkdir('lumi_build')
+
+
+@pytest.fixture
+def lumi_dut(build_dir, request):
+    dut = SbDut('testbench', default_main=True, trace=False)
+
+    dut.use(lumi)
+
+    # Add testbench
+    dut.input('lumi/testbench/testbench_lumi.sv', package='umi')
+
+    # Verilator configuration
+    dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'lumi/testbench/config.vlt',
+            package='umi')
+
+    # Build simulator
+    dut.set('option', 'builddir', build_dir / lumi.__name__)
+    with InterProcessLock(build_dir / f'{lumi.__name__}.lock'):
+        # ensure build only happens once
+        # https://github.com/pytest-dev/pytest-xdist/blob/v3.6.1/docs/how-to.rst#making-session-scoped-fixtures-execute-only-once
+        dut.build(fast=True)
+
+    yield dut
+
+    dut.terminate()
+
+
+@pytest.fixture(params=("2d", "3d"))
+def chip_topo(request):
+    return request.param