Merge pull request #135 from zeroasiccorp/ali/fixes

Fixes to fifo flex merge logic and to conform to lambdalib
zeroasiccorp · Jun 5, 2024 · 9092f21 · 9092f21
2 parents fd86f0f + 1c67e3a
commit 9092f21
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Showing 17 changed files with 19 additions and 16 deletions.
diff --git a/README.md b/README.md
@@ -556,7 +556,7 @@ to the TX of the host (and vice versa).](docs/_images/swizzle_lumi.png)
 #### nreset
 
 Asynchronous active low reset. To prevent power up and initialization issues the device 'nreset' pin must be sampled by a synchronizer with asynchronous assert and synchronous deassert logic.
-[REF](https://github.com/siliconcompiler/lambdalib/blob/main/stdlib/rtl/la_rsync.v)
+[REF](https://github.com/siliconcompiler/lambdalib/blob/main/lambdalib/auxlib/rtl/la_rsync.v)
 
 #### clk
 

diff --git a/pyproject.toml b/pyproject.toml
@@ -18,7 +18,7 @@ requires-python = ">= 3.8"
 license = {file = "LICENSE"}
 dependencies = [
     "siliconcompiler>=0.21.0",
-    "lambdalib==0.2.3"
+    "lambdalib==0.2.4"
 ]
 dynamic = [
     "version"

diff --git a/umi/lumi/rtl/lumi_rx.v b/umi/lumi/rtl/lumi_rx.v
@@ -558,6 +558,7 @@ module lumi_rx
                    // Inputs
                    .clk              (ioclk),
                    .nreset           (ionreset),
+                   .clear            (1'b0),
                    .vss              (1'b0),
                    .vdd              (1'b1),
                    .chaosmode        (1'b0),
@@ -605,6 +606,7 @@ module lumi_rx
                     // Inputs
                     .clk              (ioclk),
                     .nreset           (ionreset),
+                    .clear            (1'b0),
                     .vss              (1'b0),
                     .vdd              (1'b1),
                     .chaosmode        (1'b0),

diff --git a/umi/lumi/testbench/test_lumi.py b/umi/lumi/testbench/test_lumi.py
@@ -26,7 +26,7 @@ def build_testbench(topo="2d", trace=False):
 
     dut.use(umi)
     dut.add('option', 'library', ['lumi', 'umi'])
-    dut.add('option', 'library', 'lambdalib_stdlib')
+    dut.add('option', 'library', 'lambdalib_auxlib')
     dut.add('option', 'library', 'lambdalib_ramlib')
     dut.add('option', 'library', 'lambdalib_vectorlib')
 

diff --git a/umi/lumi/testbench/test_lumi_rnd.py b/umi/lumi/testbench/test_lumi_rnd.py
@@ -26,7 +26,7 @@ def build_testbench(topo="2d", trace=False):
 
     dut.use(umi)
     dut.add('option', 'library', ['lumi', 'umi'])
-    dut.add('option', 'library', 'lambdalib_stdlib')
+    dut.add('option', 'library', 'lambdalib_auxlib')
     dut.add('option', 'library', 'lambdalib_ramlib')
     dut.add('option', 'library', 'lambdalib_vectorlib')
 

diff --git a/umi/umi/rtl/umi_fifo_flex.v b/umi/umi/rtl/umi_fifo_flex.v
@@ -317,7 +317,7 @@ module umi_fifo_flex
 
         assign tx_mergeable = opcode_mergeable & misc_mergeable &
                               dstaddr_mergeable & srcaddr_mergeable &
-                              len_mergeable;
+                              len_mergeable & (latch_bytes != 0);
 
         reg             packet_latch_eom;
         wire            packet_boundary;
@@ -607,6 +607,7 @@ module umi_fifo_flex
                // Inputs
                .clk          (umi_in_clk),
                .nreset       (umi_in_nreset),
+               .clear        (1'b0),
                .wr_din       (fifo_din[ODW+AW+AW+CW-1:0]),
                .wr_en        (fifo_write),
                .chaosmode    (chaosmode),
@@ -639,7 +640,7 @@ module umi_fifo_flex
    assign fifo_empty              = (bypass | ~(|DEPTH)) ? 1'b1                 : fifo_empty_raw;
 
    assign umi_out_cmd[CW-1:0]     = (bypass | ~(|DEPTH)) ? latch2fifo_cmd[CW-1:0]     : fifo_dout[CW-1:0];
-   assign umi_out_dstaddr[AW-1:0] = (bypass | ~(|DEPTH)) ? latch2fifo_dstaddr[AW-1:0] : fifo_dout[CW+:AW] & 64'hFFFF_FFFF_FFFF_FFFF;
+   assign umi_out_dstaddr[AW-1:0] = (bypass | ~(|DEPTH)) ? latch2fifo_dstaddr[AW-1:0] : fifo_dout[CW+:AW] & {AW{1'b1}};
    assign umi_out_srcaddr[AW-1:0] = (bypass | ~(|DEPTH)) ? latch2fifo_srcaddr[AW-1:0] : fifo_dout[CW+AW+:AW];
    assign umi_out_data[ODW-1:0]   = (bypass | ~(|DEPTH)) ? latch2fifo_data[ODW-1:0] : fifo_dout[CW+AW+AW+:ODW];
 

diff --git a/umi/umi/testbench/test_crossbar.py b/umi/umi/testbench/test_crossbar.py
@@ -19,7 +19,7 @@ def build_testbench():
 
     dut.use(umi)
     dut.add('option', 'library', 'umi')
-    dut.add('option', 'library', 'lambdalib_stdlib')
+    dut.add('option', 'library', 'lambdalib_auxlib')
     dut.add('option', 'library', 'lambdalib_ramlib')
     dut.add('option', 'library', 'lambdalib_vectorlib')
 

diff --git a/umi/umi/testbench/test_fifo.py b/umi/umi/testbench/test_fifo.py
@@ -18,7 +18,7 @@ def build_testbench():
 
     dut.use(umi)
     dut.add('option', 'library', 'umi')
-    dut.add('option', 'library', 'lambdalib_stdlib')
+    dut.add('option', 'library', 'lambdalib_auxlib')
     dut.add('option', 'library', 'lambdalib_ramlib')
 
     # Verilator configuration

diff --git a/umi/umi/testbench/test_fifo_flex.py b/umi/umi/testbench/test_fifo_flex.py
@@ -18,7 +18,7 @@ def build_testbench(split=False):
 
     dut.use(umi)
     dut.add('option', 'library', 'umi')
-    dut.add('option', 'library', 'lambdalib_stdlib')
+    dut.add('option', 'library', 'lambdalib_auxlib')
     dut.add('option', 'library', 'lambdalib_ramlib')
 
     dut.add('option', 'define', f'SPLIT={int(split)}')

diff --git a/umi/umi/testbench/test_mem_agent.py b/umi/umi/testbench/test_mem_agent.py
@@ -17,7 +17,7 @@ def build_testbench():
 
     dut.use(umi)
     dut.add('option', 'library', 'umi')
-    dut.add('option', 'library', 'lambdalib_stdlib')
+    dut.add('option', 'library', 'lambdalib_auxlib')
     dut.add('option', 'library', 'lambdalib_ramlib')
 
     # Verilator configuration

diff --git a/umi/umi/testbench/test_regif.py b/umi/umi/testbench/test_regif.py
@@ -18,7 +18,6 @@ def build_testbench():
 
     dut.use(umi)
     dut.add('option', 'library', 'umi')
-    dut.add('option', 'library', 'lambdalib_stdlib')
     dut.add('option', 'library', 'lambdalib_ramlib')
 
     # Verilator configuration

diff --git a/umi/umi/testbench/test_umi_ram.py b/umi/umi/testbench/test_umi_ram.py
@@ -17,7 +17,7 @@ def build_testbench():
 
     dut.use(umi)
     dut.add('option', 'library', 'umi')
-    dut.add('option', 'library', 'lambdalib_stdlib')
+    dut.add('option', 'library', 'lambdalib_auxlib')
     dut.add('option', 'library', 'lambdalib_ramlib')
     dut.add('option', 'library', 'lambdalib_vectorlib')
 

diff --git a/umi/utils/rtl/tl2umi_np.v b/umi/utils/rtl/tl2umi_np.v
@@ -472,6 +472,7 @@ module tl2umi_np #(
     ) tl2umi_req_fifo (
         .clk        (clk),
         .nreset     (nreset),
+        .clear      (1'b0),
 
         .vss        (1'b0),
         .vdd        (1'b1),

diff --git a/umi/utils/testbench/tb_tl2umi_np.v b/umi/utils/testbench/tb_tl2umi_np.v
@@ -181,7 +181,7 @@ module tb_tl2umi_np #(
     // control block
     initial begin
         r = $value$plusargs("MEMHFILE=%s", memhfile);
-        $readmemh(memhfile, memory_module_.la_spram_i.ram);
+        $readmemh(memhfile, memory_module_.la_spram.ram);
         $timeformat(-9, 0, " ns", 20);
         $dumpfile("waveform.vcd");
         $dumpvars();

diff --git a/umi/utils/testbench/test_tl2umi_np.py b/umi/utils/testbench/test_tl2umi_np.py
@@ -17,7 +17,7 @@ def build():
     chip.input('utils/testbench/tb_tl2umi_np.v', package='umi')
 
     chip.add('option', 'library', 'umi')
-    chip.add('option', 'library', 'lambdalib_stdlib')
+    chip.add('option', 'library', 'lambdalib_auxlib')
     chip.add('option', 'library', 'lambdalib_ramlib')
     chip.add('option', 'library', 'lambdalib_vectorlib')
 

diff --git a/umi/utils/testbench/test_umi2axilite.py b/umi/utils/testbench/test_umi2axilite.py
@@ -19,7 +19,7 @@ def build_testbench():
     dut.use(umi)
     dut.add('option', 'library', 'umi')
     dut.add('option', 'library', 'lambdalib_ramlib')
-    dut.add('option', 'library', 'lambdalib_stdlib')
+    dut.add('option', 'library', 'lambdalib_auxlib')
     dut.add('option', 'library', 'lambdalib_vectorlib')
 
     # Verilator configuration

diff --git a/umi/utils/testbench/test_umi2tl_np.py b/umi/utils/testbench/test_umi2tl_np.py
@@ -29,7 +29,7 @@ def build_testbench(topo="2d"):
     dut.input('utils/testbench/tlmemsim.cpp', package='umi')
 
     dut.use(umi)
-    dut.add('option', 'library', ['umi', 'lambdalib_stdlib'])
+    dut.add('option', 'library', ['umi', 'lambdalib_auxlib'])
 
     # Verilator configuration
     dut.add('tool', 'verilator', 'task', 'compile', 'option', '--coverage')