Merge pull request #153 from zeroasiccorp/fix

fix sumi conversion
zeroasiccorp · Jul 31, 2024 · 93f2b26 · 93f2b26
2 parents 9b003b4 + 253bbbe
commit 93f2b26
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Showing 14 changed files with 38 additions and 37 deletions.
diff --git a/umi/lumi/__init__.py b/umi/lumi/__init__.py
@@ -13,7 +13,7 @@ def setup(chip):
     lib.add("option", "idir", "utils/rtl")
     lib.add("option", "ydir", "utils/rtl")
 
-    lib.use(umi)
+    lib.use(sumi)
 
     lib.use(auxlib)
     lib.use(ramlib)

diff --git a/umi/sumi/__init__.py b/umi/sumi/__init__.py
@@ -1,6 +1,7 @@
 from siliconcompiler import Library
 from lambdalib import auxlib, ramlib, vectorlib
 
+
 def setup(chip):
     lib = Library(chip, "sumi", package="umi", auto_enable=True)
     lib.register_source("umi", "python://umi")

diff --git a/umi/sumi/testbench/test_crossbar.py b/umi/sumi/testbench/test_crossbar.py
@@ -8,19 +8,19 @@
 import numpy as np
 from argparse import ArgumentParser
 from switchboard import UmiTxRx, random_umi_packet, delete_queue, verilator_run, SbDut
-from umi import umi
+from umi import sumi
 
 
 def build_testbench():
     dut = SbDut('testbench', trace=False, default_main=True)
 
     # Set up inputs
-    dut.input('umi/testbench/testbench_crossbar.sv', package='umi')
+    dut.input('sumi/testbench/testbench_crossbar.sv', package='umi')
 
-    dut.use(umi)
+    dut.use(sumi)
 
     # Verilator configuration
-    dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'umi/testbench/config.vlt', package='umi')
+    dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'sumi/testbench/config.vlt', package='umi')
     dut.add('tool', 'verilator', 'task', 'compile', 'option', '--prof-cfuncs')
     dut.add('tool', 'verilator', 'task', 'compile', 'option', '-CFLAGS')
     dut.add('tool', 'verilator', 'task', 'compile', 'option', '-DVL_DEBUG')

diff --git a/umi/sumi/testbench/test_fifo.py b/umi/sumi/testbench/test_fifo.py
@@ -7,19 +7,19 @@
 import numpy as np
 from argparse import ArgumentParser
 from switchboard import SbDut, UmiTxRx, delete_queue, verilator_run
-from umi import umi
+from umi import sumi
 
 
 def build_testbench():
     dut = SbDut('testbench', trace=False, default_main=True)
 
     # Set up inputs
-    dut.input('umi/testbench/testbench_fifo.sv', package='umi')
+    dut.input('sumi/testbench/testbench_fifo.sv', package='umi')
 
-    dut.use(umi)
+    dut.use(sumi)
 
     # Verilator configuration
-    dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'umi/testbench/config.vlt', package='umi')
+    dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'sumi/testbench/config.vlt', package='umi')
 #    dut.set('option', 'relax', True)
     dut.add('tool', 'verilator', 'task', 'compile', 'option', '--prof-cfuncs')
     dut.add('tool', 'verilator', 'task', 'compile', 'option', '-CFLAGS')

diff --git a/umi/sumi/testbench/test_fifo_flex.py b/umi/sumi/testbench/test_fifo_flex.py
@@ -7,21 +7,21 @@
 import numpy as np
 from argparse import ArgumentParser
 from switchboard import SbDut, UmiTxRx, delete_queue, verilator_run
-from umi import umi
+from umi import sumi
 
 
 def build_testbench(split=False):
     dut = SbDut('testbench', trace=False, default_main=True)
 
     # Set up inputs
-    dut.input('umi/testbench/testbench_fifo_flex.sv', package='umi')
+    dut.input('sumi/testbench/testbench_fifo_flex.sv', package='umi')
 
-    dut.use(umi)
+    dut.use(sumi)
 
     dut.add('option', 'define', f'SPLIT={int(split)}')
 
     # Verilator configuration
-    dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'umi/testbench/config.vlt', package='umi')
+    dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'sumi/testbench/config.vlt', package='umi')
 #    dut.set('option', 'relax', True)
     dut.add('tool', 'verilator', 'task', 'compile', 'option', '--prof-cfuncs')
     dut.add('tool', 'verilator', 'task', 'compile', 'option', '-CFLAGS')

diff --git a/umi/sumi/testbench/test_mem_agent.py b/umi/sumi/testbench/test_mem_agent.py
@@ -6,19 +6,19 @@
 import numpy as np
 from argparse import ArgumentParser
 from switchboard import SbDut, UmiTxRx, delete_queue, verilator_run
-from umi import umi
+from umi import sumi
 
 
 def build_testbench():
     dut = SbDut('testbench', trace=False, default_main=True)
 
     # Set up inputs
-    dut.input('umi/testbench/testbench_mem_agent.sv', package='umi')
+    dut.input('sumi/testbench/testbench_mem_agent.sv', package='umi')
 
-    dut.use(umi)
+    dut.use(sumi)
 
     # Verilator configuration
-    dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'umi/testbench/config.vlt', package='umi')
+    dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'sumi/testbench/config.vlt', package='umi')
 #    dut.set('option', 'relax', True)
     dut.add('tool', 'verilator', 'task', 'compile', 'option', '--prof-cfuncs')
     dut.add('tool', 'verilator', 'task', 'compile', 'option', '-CFLAGS')

diff --git a/umi/sumi/testbench/test_regif.py b/umi/sumi/testbench/test_regif.py
@@ -7,19 +7,19 @@
 import numpy as np
 from argparse import ArgumentParser
 from switchboard import SbDut, UmiTxRx, delete_queue, verilator_run
-from umi import umi
+from umi import sumi
 
 
 def build_testbench():
     dut = SbDut('testbench', trace=False, default_main=True)
 
     # Set up inputs
-    dut.input('umi/testbench/testbench_regif.sv', package='umi')
+    dut.input('sumi/testbench/testbench_regif.sv', package='umi')
 
-    dut.use(umi)
+    dut.use(sumi)
 
     # Verilator configuration
-    dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'umi/testbench/config.vlt', package='umi')
+    dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'sumi/testbench/config.vlt', package='umi')
 #    dut.set('option', 'relax', True)
     dut.add('tool', 'verilator', 'task', 'compile', 'option', '--prof-cfuncs')
     dut.add('tool', 'verilator', 'task', 'compile', 'option', '-CFLAGS')

diff --git a/umi/sumi/testbench/test_umi_ram.py b/umi/sumi/testbench/test_umi_ram.py
@@ -6,19 +6,19 @@
 import numpy as np
 from argparse import ArgumentParser
 from switchboard import SbDut, UmiTxRx, verilator_run
-from umi import umi
+from umi import sumi
 
 
 def build_testbench():
     dut = SbDut('testbench', trace=False, default_main=True)
 
     # Set up inputs
-    dut.input('umi/testbench/testbench_umi_ram.sv', package='umi')
+    dut.input('sumi/testbench/testbench_umi_ram.sv', package='umi')
 
-    dut.use(umi)
+    dut.use(sumi)
 
     # Verilator configuration
-    dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'umi/testbench/config.vlt', package='umi')
+    dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'sumi/testbench/config.vlt', package='umi')
 #    dut.set('option', 'relax', True)
     dut.add('tool', 'verilator', 'task', 'compile', 'option', '--prof-cfuncs')
     dut.add('tool', 'verilator', 'task', 'compile', 'option', '-CFLAGS')

diff --git a/umi/utils/testbench/test_tl2umi_np.py b/umi/utils/testbench/test_tl2umi_np.py
@@ -3,12 +3,12 @@
 from siliconcompiler import Chip
 from siliconcompiler.flows import dvflow
 from siliconcompiler.package import path as sc_path
-from umi import umi
+from umi import sumi
 
 
 def build():
     chip = Chip('tb_tl2umi_np')
-    chip.use(umi)
+    chip.use(sumi)
     chip.use(dvflow, tool='icarus')
 
     chip.set('option', 'flow', 'dvflow')

diff --git a/umi/utils/testbench/test_umi2apb.py b/umi/utils/testbench/test_umi2apb.py
@@ -6,14 +6,14 @@
 import random
 import numpy as np
 from switchboard import SbDut, UmiTxRx, verilator_run
-from umi import umi
+from umi import sumi
 
 
 def build_testbench(dut):
     # Set up inputs
     dut.input('utils/testbench/testbench_umi2apb.sv', package='umi')
 
-    dut.use(umi)
+    dut.use(sumi)
 
     # Verilator configuration
     dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'utils/testbench/config.vlt',

diff --git a/umi/utils/testbench/test_umi2axilite.py b/umi/utils/testbench/test_umi2axilite.py
@@ -7,7 +7,7 @@
 import numpy as np
 from argparse import ArgumentParser
 from switchboard import SbDut, UmiTxRx, delete_queue, verilator_run
-from umi import umi
+from umi import sumi
 
 
 def build_testbench():
@@ -16,7 +16,7 @@ def build_testbench():
     # Set up inputs
     dut.input('utils/testbench/testbench_umi2axilite.sv', package='umi')
 
-    dut.use(umi)
+    dut.use(sumi)
 
     # Verilator configuration
     dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config',

diff --git a/umi/utils/testbench/test_umi2tl_np.py b/umi/utils/testbench/test_umi2tl_np.py
@@ -8,7 +8,7 @@
 from argparse import ArgumentParser
 from switchboard import SbDut, UmiTxRx, delete_queue, verilator_run
 from siliconcompiler.package import path as sc_path
-from umi import umi
+from umi import sumi
 
 
 def build_testbench(topo="2d"):
@@ -28,7 +28,7 @@ def build_testbench(topo="2d"):
     dut.input('utils/testbench/testbench_umi2tl_np.cc', package='umi')
     dut.input('utils/testbench/tlmemsim.cpp', package='umi')
 
-    dut.use(umi)
+    dut.use(sumi)
 
     # Verilator configuration
     dut.add('tool', 'verilator', 'task', 'compile', 'option', '--coverage')

diff --git a/umi/utils/testbench/test_umi_address_remap.py b/umi/utils/testbench/test_umi_address_remap.py
@@ -5,7 +5,7 @@
 import random
 from argparse import ArgumentParser
 from switchboard import SbDut, UmiTxRx, delete_queue, verilator_run, random_umi_packet
-from umi import umi
+from umi import sumi
 
 
 def build_testbench(topo="2d"):
@@ -22,7 +22,7 @@ def build_testbench(topo="2d"):
     else:
         raise ValueError('Invalid topology')
 
-    dut.use(umi)
+    dut.use(sumi)
 
     # Verilator configuration
     dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'utils/testbench/config.vlt', package='umi')

diff --git a/umi/utils/testbench/test_umi_packet_merge_greedy.py b/umi/utils/testbench/test_umi_packet_merge_greedy.py
@@ -4,7 +4,7 @@
 
 from argparse import ArgumentParser
 from switchboard import SbDut, UmiTxRx, delete_queue, verilator_run, random_umi_packet
-from umi import umi
+from umi import sumi
 
 
 def build_testbench(topo="2d"):
@@ -23,7 +23,7 @@ def build_testbench(topo="2d"):
 
     dut.input('utils/testbench/testbench_umi_packet_merge_greedy.cc', package='umi')
 
-    dut.use(umi)
+    dut.use(sumi)
 
     # Verilator configuration
     dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'utils/testbench/config.vlt', package='umi')