Merge branch 'main' into ali/umi_fifo_flex_merge

zeroasiccorp · Feb 16, 2024 · b6c2f6e · b6c2f6e
2 parents 27ac4da + f14aee3
commit b6c2f6e
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Showing 31 changed files with 168 additions and 106 deletions.
diff --git a/.github/dependabot.yml b/.github/dependabot.yml
@@ -0,0 +1,11 @@
+version: 2
+updates:
+  # Maintain dependencies for GitHub Actions
+  - package-ecosystem: "github-actions"
+    directory: "/"
+    schedule:
+      interval: "weekly"
+    groups:
+      actions:
+        patterns:
+          - "*"
diff --git a/.github/workflows/bin/collect_tests.py b/.github/workflows/bin/collect_tests.py
@@ -0,0 +1,16 @@
+import json
+import os
+
+
+if __name__ == "__main__":
+    script_dir = os.path.dirname(os.path.abspath(__file__))
+    repo_dir = os.path.abspath(os.path.join(script_dir, '..', '..', '..'))
+    tests = []
+    for dirpath, dirnames, filenames in os.walk(repo_dir):
+        for f in filenames:
+            if f.startswith("test_"):
+                tests.append(os.path.join(dirpath, f))
+
+    tests_rel = [os.path.relpath(p, repo_dir) for p in tests]
+
+    print(json.dumps({"testbench": tests_rel}))
diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
@@ -0,0 +1,54 @@
+name: Testbench CI
+on:
+  # Runs on all PRs
+  pull_request:
+  # Manual Dispatch
+  workflow_dispatch:
+
+jobs:
+  get_testbenches:
+    name: 'Get testbenches'
+
+    runs-on: ubuntu-latest
+
+    outputs:
+      testbenches: ${{ steps.tests.outputs.tests }}
+
+    steps:
+      - name: Checkout repository
+        uses: actions/checkout@v4
+
+      - name: Collect testbenches
+        id: tests
+        run: |
+          echo "tests=$(python3 .github/workflows/bin/collect_tests.py)" >> $GITHUB_OUTPUT
+
+  testbench:
+    needs: get_testbenches
+    strategy:
+      fail-fast: false
+      matrix: ${{ fromJson(needs.get_testbenches.outputs.testbenches) }}
+
+    timeout-minutes: 10
+    runs-on: ubuntu-latest
+    container:
+      image: ghcr.io/zeroasiccorp/sbtest:latest
+
+    steps:
+      - name: Check out UMI
+        uses: actions/checkout@v4
+        with:
+          submodules: recursive
+
+      - name: Install requirements
+        run: |
+          python3 -m venv .venv
+          . .venv/bin/activate
+          python3 -m pip install --upgrade pip
+          python3 -m pip install switchboard-hw
+
+      - name: Run ${{ matrix.testbench }}
+        run: |
+          . .venv/bin/activate
+          cd $(dirname "${{ matrix.testbench }}")
+          ./$(basename "${{ matrix.testbench }}")
diff --git a/.gitignore b/.gitignore
@@ -9,6 +9,9 @@
 # test results
 *.q
 *.vcd
+*.fst
+build/
+gmon.out
 
 ######################
 # Emacs/vim/gedit backup files

diff --git a/.gitmodules b/.gitmodules
@@ -1,6 +1,3 @@
 [submodule "submodules/lambdalib"]
 	path = submodules/lambdalib
 	url = [email protected]:siliconcompiler/lambdalib.git
-[submodule "submodules/switchboard"]
-	path = submodules/switchboard
-	url = [email protected]:zeroasiccorp/switchboard.git
diff --git a/lumi/rtl/lumi.v b/lumi/rtl/lumi.v
@@ -23,22 +23,23 @@
  ******************************************************************************/
 
 module lumi
-  #(parameter TARGET = "DEFAULT",                          // compiler target
+  #(// for development
+    parameter DW = 128,                                    // umi packet width
+    parameter CW = 32,                                     // umi packet width
+    parameter AW = 64,                                     // address width
+    parameter RW = 64,                                     // register width
+    parameter IDW = 16,                                    // chipid width
+    parameter IOW = 64,                                    // phy IO width
+    // end development
+    parameter TARGET = "DEFAULT",                          // compiler target
     parameter IDOFFSET = 40,                               // chip ID address offset
     parameter GRPOFFSET = 24,                              // group address offset
     parameter GRPAW = 8,                                   // group address width
     parameter GRPID = 0,                                   // group ID
     parameter ASYNCFIFODEPTH = 8,                          // depth of async fifo
     parameter RXFIFOW = 8,                                 // width of Rx fifo (in bits) - cannot be smaller than IOW!!!
     parameter NFIFO = IOW/RXFIFOW,                         // number of parallel fifo's
-    parameter CRDTDEPTH = 1+((DW+AW+AW+CW)/RXFIFOW)/NFIFO, // total fifo depth, eq is minimum
-    // for development
-    parameter DW = 128,                                    // umi packet width
-    parameter CW = 32,                                     // umi packet width
-    parameter AW = 64,                                     // address width
-    parameter RW = 64,                                     // register width
-    parameter IDW = 16,                                    // chipid width
-    parameter IOW = 64                                     // phy IO width
+    parameter CRDTDEPTH = 1+((DW+AW+AW+CW)/RXFIFOW)/NFIFO  // total fifo depth, eq is minimum
     )
    (// host/device selector
     input            devicemode,      // 1=device, 0=host
@@ -496,5 +497,5 @@ module lumi
 
 endmodule // clink
 // Local Variables:
-// verilog-library-directories:("." "../../submodules/oh/stdlib/rtl" "../../../umi/umi/rtl" )
+// verilog-library-directories:("." "../../umi/rtl" )
 // End:
diff --git a/lumi/rtl/lumi_rx.v b/lumi/rtl/lumi_rx.v
@@ -1229,5 +1229,5 @@ module lumi_rx
 
 endmodule
 // Local Variables:
-// verilog-library-directories:("." "../../umi/rtl/" "../../../lambdalib/ramlib/rtl/")
+// verilog-library-directories:("." "../../umi/rtl/")
 // End:
diff --git a/lumi/rtl/lumi_tx.v b/lumi/rtl/lumi_tx.v
@@ -624,5 +624,5 @@ module lumi_tx
 
 endmodule
 // Local Variables:
-// verilog-library-directories:("." "../../umi/rtl/" "../submodules/lambdalib/stdlib/rtl")
+// verilog-library-directories:("." "../../umi/rtl/")
 // End:
diff --git a/lumi/testbench/test_lumi.py b/lumi/testbench/test_lumi.py
@@ -27,11 +27,9 @@ def build_testbench(topo="2d", trace=False):
     else:
         raise ValueError('Invalid topology')
 
-    dut.input(EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilator' / 'testbench.cc')
     for option in ['ydir', 'idir']:
         dut.add('option', option, EX_DIR / 'rtl')
         dut.add('option', option, EX_DIR / '..' / 'umi' / 'rtl')
-        dut.add('option', option, EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilog')
         dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'ramlib' / 'rtl')
         dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'stdlib' / 'rtl')
         dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'vectorlib' / 'rtl')

diff --git a/lumi/testbench/test_lumi_rnd.py b/lumi/testbench/test_lumi_rnd.py
@@ -27,11 +27,9 @@ def build_testbench(topo="2d", trace=False):
     else:
         raise ValueError('Invalid topology')
 
-    dut.input(EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilator' / 'testbench.cc')
     for option in ['ydir', 'idir']:
         dut.add('option', option, EX_DIR / 'rtl')
         dut.add('option', option, EX_DIR / '..' / 'umi' / 'rtl')
-        dut.add('option', option, EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilog')
         dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'ramlib' / 'rtl')
         dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'stdlib' / 'rtl')
         dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'vectorlib' / 'rtl')
@@ -67,8 +65,7 @@ def main(topo="2d", vldmode="2", rdymode="2", trace=False, host2dut="host2dut_0.
             ('hostdly', hostdly),
             ('devdly', devdly)
         ],
-        trace=trace,
-        args=['+verilator+seed+0']
+        trace=trace
     )
 
     # instantiate TX and RX queues.  note that these can be instantiated without

diff --git a/lumi/testbench/testbench_lumi.sv b/lumi/testbench/testbench_lumi.sv
@@ -387,28 +387,28 @@ module testbench (
               .vss              (),                      // Templated
               .vdd              ());                     // Templated
 
-   umiram #(.ADDR_WIDTH(10),
-            .DATA_WIDTH(DW),
-            .DW(DW),
-            .AW(AW),
-            .CW(CW),
-            .ATOMIC_WIDTH(64))
-   umiram_i(// Outputs
-            .udev_req_ready(udev_req_ready),
-            .udev_resp_valid(udev_resp_valid),
-            .udev_resp_cmd(udev_resp_cmd[CW-1:0]),
-            .udev_resp_dstaddr(udev_resp_dstaddr[AW-1:0]),
-            .udev_resp_srcaddr(udev_resp_srcaddr[AW-1:0]),
-            .udev_resp_data(udev_resp_data[DW-1:0]),
-            // Inputs
-            .clk(clk),
-            .udev_req_valid(udev_req_valid),
-            .udev_req_cmd(udev_req_cmd[CW-1:0]),
-            .udev_req_dstaddr(udev_req_dstaddr[AW-1:0]),
-            .udev_req_srcaddr(udev_req_srcaddr[AW-1:0]),
-            .udev_req_data(udev_req_data[DW-1:0]),
-            .udev_resp_ready(udev_resp_ready)
-            /*AUTOINST*/);
+   umi_mem_agent #(.DW(DW),
+                   .AW(AW),
+                   .CW(CW),
+                   .CTRLW(8))
+   umi_mem_agent_i(.sram_ctrl           (8'b010_01_0_0_0),
+                   /*AUTOINST*/
+                   // Outputs
+                   .udev_req_ready      (udev_req_ready),
+                   .udev_resp_valid     (udev_resp_valid),
+                   .udev_resp_cmd       (udev_resp_cmd[CW-1:0]),
+                   .udev_resp_dstaddr   (udev_resp_dstaddr[AW-1:0]),
+                   .udev_resp_srcaddr   (udev_resp_srcaddr[AW-1:0]),
+                   .udev_resp_data      (udev_resp_data[DW-1:0]),
+                   // Inputs
+                   .clk                 (clk),
+                   .nreset              (nreset),
+                   .udev_req_valid      (udev_req_valid),
+                   .udev_req_cmd        (udev_req_cmd[CW-1:0]),
+                   .udev_req_dstaddr    (udev_req_dstaddr[AW-1:0]),
+                   .udev_req_srcaddr    (udev_req_srcaddr[AW-1:0]),
+                   .udev_req_data       (udev_req_data[DW-1:0]),
+                   .udev_resp_ready     (udev_resp_ready));
 
             // Initialize UMI
    integer valid_mode, ready_mode;
@@ -469,7 +469,7 @@ module testbench (
 
 endmodule
 // Local Variables:
-// verilog-library-directories:("../rtl" "../../submodules/switchboard/examples/common/verilog/" )
+// verilog-library-directories:("../rtl" "../../umi/rtl" )
 // End:
 
 `default_nettype wire
diff --git a/submodules/switchboard b/submodules/switchboard
diff --git a/umi/rtl/umi_endpoint.v b/umi/rtl/umi_endpoint.v
@@ -330,5 +330,5 @@ module umi_endpoint
 
 endmodule // umi_endpoint
 // Local Variables:
-// verilog-library-directories:("." "../../submodules/lambdalib/stdlib/rtl")
+// verilog-library-directories:(".")
 // End:
diff --git a/umi/rtl/umi_fifo.v b/umi/rtl/umi_fifo.v
@@ -127,5 +127,5 @@ module umi_fifo
 
 endmodule // clink_fifo
 // Local Variables:
-// verilog-library-directories:("." "../../../lambdalib/ramlib/rtl")
+// verilog-library-directories:(".")
 // End:
diff --git a/umi/rtl/umi_fifo_flex.v b/umi/rtl/umi_fifo_flex.v
@@ -653,5 +653,5 @@ module umi_fifo_flex
 
 endmodule // clink_fifo
 // Local Variables:
-// verilog-library-directories:("." "../../../lambdalib/ramlib/rtl")
+// verilog-library-directories:(".")
 // End:
diff --git a/umi/rtl/umi_mem_agent.v b/umi/rtl/umi_mem_agent.v
@@ -286,5 +286,5 @@ module umi_mem_agent
 
 endmodule // ebrick_core
 // Local Variables:
-// verilog-library-directories:("./" "../umi/rtl" "../../submodules/lambdalib/ramlib/rtl/")
+// verilog-library-directories:("./")
 // End:
diff --git a/umi/testbench/dut_umi_fifo.v b/umi/testbench/dut_umi_fifo.v
@@ -86,5 +86,5 @@ module dut_umi_fifo
 
 endmodule // testbench
 // Local Variables:
-// verilog-library-directories:("../rtl" "../../../lambdalib/stdlib/rtl")
+// verilog-library-directories:("../rtl")
 // End:
diff --git a/umi/testbench/dut_umi_fifo_flex.v b/umi/testbench/dut_umi_fifo_flex.v
@@ -90,5 +90,5 @@ module dut_umi_fifo_flex
 
 endmodule // testbench
 // Local Variables:
-// verilog-library-directories:("../rtl" "../../../lambdalib/stdlib/rtl")
+// verilog-library-directories:("../rtl")
 // End:
diff --git a/umi/testbench/test_crossbar.py b/umi/testbench/test_crossbar.py
@@ -14,21 +14,19 @@
 THIS_DIR = Path(__file__).resolve().parent
 
 def build_testbench():
-    dut = SbDut('testbench')
+    dut = SbDut('testbench', default_main=True)
 
     EX_DIR = Path('..')
     EX_DIR = EX_DIR.resolve()
 
     # Set up inputs
     dut.input('testbench_crossbar.sv')
 
-    dut.input(EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilator' / 'testbench.cc')
     for option in ['ydir', 'idir']:
         dut.add('option', option, EX_DIR / 'rtl')
-        dut.add('option', option, EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilog')
-        dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'ramlib' / 'rtl')
-        dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'stdlib' / 'rtl')
-        dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'vectorlib' / 'rtl')
+        dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'ramlib' / 'rtl')
+        dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'stdlib' / 'rtl')
+        dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'vectorlib' / 'rtl')
 
     # Verilator configuration
     vlt_config = EX_DIR / 'testbench' / 'config.vlt'

diff --git a/umi/testbench/test_fifo.py b/umi/testbench/test_fifo.py
@@ -13,21 +13,19 @@
 
 
 def build_testbench():
-    dut = SbDut('testbench')
+    dut = SbDut('testbench', default_main=True)
 
     EX_DIR = Path('..')
     EX_DIR = EX_DIR.resolve()
 
     # Set up inputs
     dut.input('testbench_fifo.sv')
 
-    dut.input(EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilator' / 'testbench.cc')
     for option in ['ydir', 'idir']:
         dut.add('option', option, EX_DIR / 'rtl')
-        dut.add('option', option, EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilog')
-        dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'ramlib' / 'rtl')
-        dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'stdlib' / 'rtl')
-        dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'vectorlib' / 'rtl')
+        dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'ramlib' / 'rtl')
+        dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'stdlib' / 'rtl')
+        dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'vectorlib' / 'rtl')
 
     # Verilator configuration
     vlt_config = EX_DIR / 'testbench' / 'config.vlt'

diff --git a/umi/testbench/test_fifo_flex.py b/umi/testbench/test_fifo_flex.py
@@ -13,18 +13,16 @@
 
 
 def build_testbench():
-    dut = SbDut('testbench')
+    dut = SbDut('testbench', default_main=True)
 
     EX_DIR = Path('..')
     EX_DIR = EX_DIR.resolve()
 
     # Set up inputs
     dut.input('testbench_fifo_flex.sv')
 
-    dut.input(EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilator' / 'testbench.cc')
     for option in ['ydir', 'idir']:
         dut.add('option', option, EX_DIR / 'rtl')
-        dut.add('option', option, EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilog')
         dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'ramlib' / 'rtl')
         dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'stdlib' / 'rtl')
         dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'vectorlib' / 'rtl')

diff --git a/umi/testbench/test_mem_agent.py b/umi/testbench/test_mem_agent.py
@@ -13,21 +13,19 @@
 
 
 def build_testbench():
-    dut = SbDut('testbench')
+    dut = SbDut('testbench', default_main=True)
 
     EX_DIR = Path('..')
     EX_DIR = EX_DIR.resolve()
 
     # Set up inputs
     dut.input('testbench_mem_agent.sv')
 
-    dut.input(EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilator' / 'testbench.cc')
     for option in ['ydir', 'idir']:
         dut.add('option', option, EX_DIR / 'rtl')
-        dut.add('option', option, EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilog')
-        dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'ramlib' / 'rtl')
-        dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'stdlib' / 'rtl')
-        dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'vectorlib' / 'rtl')
+        dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'ramlib' / 'rtl')
+        dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'stdlib' / 'rtl')
+        dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'vectorlib' / 'rtl')
 
     # Verilator configuration
     vlt_config = EX_DIR / 'testbench' / 'config.vlt'