TYPE->PROP

zeroasiccorp · Jul 30, 2024 · befbb27 · befbb27
1 parent ff7236b
commit befbb27
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Showing 4 changed files with 8 additions and 8 deletions.
diff --git a/umi/lumi/rtl/lumi_rx.v b/umi/lumi/rtl/lumi_rx.v
@@ -550,7 +550,7 @@ module lumi_rx
                       .CHAOS(0),         // generates random full logic when set
                       .CTRLW(1),         // width of asic ctrl interface
                       .TESTW(1),         // width of asic test interface
-                      .TYPE("DEFAULT"))  // Pass through variable for hard macro
+                      .PROP("DEFAULT"))  // Pass through variable for hard macro
         req_fifo_i(// Outputs
                    .wr_full          (req_fifo_full[j]),
                    .rd_dout          (req_fifo_dout[j*RXFIFOW+:RXFIFOW]),
@@ -598,7 +598,7 @@ module lumi_rx
                       .CHAOS(0),         // generates random full logic when set
                       .CTRLW(1),         // width of asic ctrl interface
                       .TESTW(1),         // width of asic test interface
-                      .TYPE("DEFAULT"))  // Pass through variable for hard macro
+                      .PROP("DEFAULT"))  // Pass through variable for hard macro
         resp_fifo_i(// Outputs
                     .wr_full          (resp_fifo_full[k]),
                     .rd_dout          (resp_fifo_dout[k*RXFIFOW+:RXFIFOW]),
@@ -663,7 +663,7 @@ module lumi_rx
                   .CHAOS(0),  // generates random full logic when set
                   .CTRLW(1),  // width of asic ctrl interface
                   .TESTW(1),  // width of asic test interface
-                  .TYPE("DEFAULT")) // Pass through variable for hard macro
+                  .PROP("DEFAULT")) // Pass through variable for hard macro
    lnk_fifo_i(// Outputs
               .wr_full          (),
               .rd_dout          (lnk_fifo_dout[CW-1:0]),
@@ -782,7 +782,7 @@ module lumi_rx
                   .CHAOS(0),              // generates random full logic when set
                   .CTRLW(1),              // width of asic ctrl interface
                   .TESTW(1),              // width of asic test interface
-                  .TYPE("DEFAULT"))       // Pass through variable for hard macro
+                  .PROP("DEFAULT"))       // Pass through variable for hard macro
    req_syncfifo_i(// Outputs
                   .wr_full          (sync_fifo_full[0]),
                   .rd_dout          (sync_fifo_dout[IOW-1:0]),
@@ -810,7 +810,7 @@ module lumi_rx
                   .CHAOS(0),              // generates random full logic when set
                   .CTRLW(1),              // width of asic ctrl interface
                   .TESTW(1),              // width of asic test interface
-                  .TYPE("DEFAULT"))       // Pass through variable for hard macro
+                  .PROP("DEFAULT"))       // Pass through variable for hard macro
    resp_syncfifo_i(// Outputs
                    .wr_full          (sync_fifo_full[1]),
                    .rd_dout          (sync_fifo_dout[2*IOW-1:IOW]),

diff --git a/umi/lumi/rtl/lumi_tx.v b/umi/lumi/rtl/lumi_tx.v
@@ -597,7 +597,7 @@ module lumi_tx
                   .CHAOS(0),         // generates random full logic when set
                   .CTRLW(1),         // width of asic ctrl interface
                   .TESTW(1),         // width of asic test interface
-                  .TYPE("DEFAULT"))  // Pass through variable for hard macro
+                  .PROP("DEFAULT"))  // Pass through variable for hard macro
    phy_fifo_i(// Outputs
               .wr_full          (phy_fifo_full),
               .rd_dout          (phy_txdata[IOW-1:0]),

diff --git a/umi/umi/rtl/umi_mem_agent.v b/umi/umi/rtl/umi_mem_agent.v
@@ -260,7 +260,7 @@ module umi_mem_agent
 
    la_spram #(.DW    (DW),               // Memory width
               .AW    ($clog2(RAMDEPTH)), // Address width (derived)
-              .TYPE  (SRAMTYPE),         // Pass through variable for hard macro
+              .PROP  (SRAMTYPE),         // Pass through variable for hard macro
               .CTRLW (CTRLW),            // Width of asic ctrl interface
               .TESTW (128)               // Width of asic test interface
               )

diff --git a/umi/utils/rtl/tl2umi_np.v b/umi/utils/rtl/tl2umi_np.v
@@ -468,7 +468,7 @@ module tl2umi_np #(
     la_syncfifo #(
         .DW     (CW + AW + AW + DW),
         .DEPTH  (2),
-        .TYPE   ("DEFAULT")
+        .PROP   ("DEFAULT")
     ) tl2umi_req_fifo (
         .clk        (clk),
         .nreset     (nreset),