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Merge branch 'core-v-polara-apu' of https://github.com/PolyMTL-Gr2m/ara…
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elisabethumblet committed Nov 14, 2023
2 parents 575fa15 + 506e8eb commit 9c45222
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166 changes: 166 additions & 0 deletions openpiton/Flist.ariane
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// Copyright (c) 2018 ETH Zurich, University of Bologna
// All rights reserved.
//
// This code is under development and not yet released to the public.
// Until it is released, the code is under the copyright of ETH Zurich and
// the University of Bologna, and may contain confidential and/or unpublished
// work. Any reuse/redistribution is strictly forbidden without written
// permission from ETH Zurich.
//
// Bug fixes and contributions will eventually be released under the
// SolderPad open hardware license in the context of the PULP platform
// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the
// University of Bologna.
//
// Author: Michael Schaffner <[email protected]>, ETH Zurich
// Date: 15.08.2018
// Description: File list for OpenPiton flow
+incdir+$ARIANE_ROOT/vendor/pulp-platform/common_cells/include/
+incdir+$ARIANE_ROOT/common/local/util/
+incdir+$ARIANE_ROOT/corev_apu/register_interface/include/

$ARIANE_ROOT/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv
$ARIANE_ROOT/core/include/riscv_pkg.sv
$ARIANE_ROOT/corev_apu/riscv-dbg/src/dm_pkg.sv
$ARIANE_ROOT/core/include/ariane_dm_pkg.sv
$ARIANE_ROOT/vendor/openhwgroup/cvfpu/src/fpnew_pkg.sv
$ARIANE_ROOT/core/include/ariane_pkg.sv
$ARIANE_ROOT/core/include/acc_pkg.sv
$ARIANE_ROOT/corev_apu/tb/ariane_soc_pkg.sv
$ARIANE_ROOT/vendor/pulp-platform/axi/src/axi_pkg.sv
$ARIANE_ROOT/corev_apu/tb/ariane_axi_pkg.sv
$ARIANE_ROOT/core/include/wt_cache_pkg.sv
$ARIANE_ROOT/corev_apu/tb/axi_intf.sv
$ARIANE_ROOT/core/include/cvxif_pkg.sv
$ARIANE_ROOT/vendor/pulp-platform/common_cells/src/cf_math_pkg.sv
$ARIANE_ROOT/core/include/instr_tracer_pkg.sv
$ARIANE_ROOT/core/cvxif_example/include/cvxif_instr_pkg.sv
$ARIANE_ROOT/core/acc_dispatcher.sv
$ARIANE_ROOT/corev_apu/rv_plic/rtl/rv_plic_reg_pkg.sv
$ARIANE_ROOT/common/local/util/sram.sv
$ARIANE_ROOT/vendor/pulp-platform/common_cells/src/deprecated/rrarbiter.sv
$ARIANE_ROOT/vendor/pulp-platform/common_cells/src/deprecated/fifo_v1.sv
$ARIANE_ROOT/vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv
$ARIANE_ROOT/vendor/pulp-platform/common_cells/src/fifo_v3.sv
$ARIANE_ROOT/vendor/pulp-platform/common_cells/src/shift_reg.sv
$ARIANE_ROOT/vendor/pulp-platform/common_cells/src/lfsr_8bit.sv
$ARIANE_ROOT/vendor/pulp-platform/common_cells/src/lfsr.sv
$ARIANE_ROOT/vendor/pulp-platform/common_cells/src/lzc.sv
$ARIANE_ROOT/vendor/pulp-platform/common_cells/src/exp_backoff.sv
$ARIANE_ROOT/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv
$ARIANE_ROOT/vendor/pulp-platform/common_cells/src/rstgen_bypass.sv
$ARIANE_ROOT/vendor/pulp-platform/common_cells/src/cdc_2phase.sv
$ARIANE_ROOT/vendor/pulp-platform/common_cells/src/unread.sv
$ARIANE_ROOT/vendor/pulp-platform/common_cells/src/popcount.sv
$ARIANE_ROOT/corev_apu/axi_mem_if/src/axi2mem.sv
$ARIANE_ROOT/vendor/pulp-platform/tech_cells_generic/src/deprecated/cluster_clk_cells.sv
$ARIANE_ROOT/vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_clk_cells.sv
$ARIANE_ROOT/common/local/util/tc_sram_wrapper.sv
$ARIANE_ROOT/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv
$ARIANE_ROOT/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_clk.sv
$ARIANE_ROOT/core/cache_subsystem/axi_adapter.sv
$ARIANE_ROOT/core/alu.sv
$ARIANE_ROOT/core/fpu_wrap.sv
$ARIANE_ROOT/../ara/openpiton/ariane.sv
$ARIANE_ROOT/core/cva6.sv
$ARIANE_ROOT/core/branch_unit.sv
$ARIANE_ROOT/core/compressed_decoder.sv
$ARIANE_ROOT/core/controller.sv
$ARIANE_ROOT/core/csr_buffer.sv
$ARIANE_ROOT/core/csr_regfile.sv
$ARIANE_ROOT/core/decoder.sv
$ARIANE_ROOT/core/ex_stage.sv
$ARIANE_ROOT/core/frontend/btb.sv
$ARIANE_ROOT/core/frontend/bht.sv
$ARIANE_ROOT/core/frontend/ras.sv
$ARIANE_ROOT/core/frontend/instr_scan.sv
$ARIANE_ROOT/core/frontend/instr_queue.sv
$ARIANE_ROOT/core/frontend/frontend.sv
$ARIANE_ROOT/core/id_stage.sv
$ARIANE_ROOT/core/instr_realign.sv
$ARIANE_ROOT/core/issue_read_operands.sv
$ARIANE_ROOT/core/issue_stage.sv
$ARIANE_ROOT/core/load_unit.sv
$ARIANE_ROOT/core/load_store_unit.sv
$ARIANE_ROOT/core/lsu_bypass.sv
$ARIANE_ROOT/core/mmu_sv39/mmu.sv
$ARIANE_ROOT/core/mult.sv
$ARIANE_ROOT/core/multiplier.sv
$ARIANE_ROOT/core/serdiv.sv
$ARIANE_ROOT/core/perf_counters.sv
$ARIANE_ROOT/core/mmu_sv39/ptw.sv
$ARIANE_ROOT/core/ariane_regfile_ff.sv
$ARIANE_ROOT/core/re_name.sv
$ARIANE_ROOT/core/scoreboard.sv
$ARIANE_ROOT/core/store_buffer.sv
$ARIANE_ROOT/core/amo_buffer.sv
$ARIANE_ROOT/core/store_unit.sv
$ARIANE_ROOT/core/mmu_sv39/tlb.sv
$ARIANE_ROOT/core/commit_stage.sv
$ARIANE_ROOT/core/cache_subsystem/wt_dcache_ctrl.sv
$ARIANE_ROOT/core/cache_subsystem/wt_dcache_mem.sv
$ARIANE_ROOT/core/cache_subsystem/wt_dcache_missunit.sv
$ARIANE_ROOT/core/cache_subsystem/wt_dcache_wbuffer.sv
$ARIANE_ROOT/core/cache_subsystem/wt_dcache.sv
$ARIANE_ROOT/core/cache_subsystem/cva6_icache.sv
$ARIANE_ROOT/core/cache_subsystem/cva6_icache_axi_wrapper.sv
$ARIANE_ROOT/core/cache_subsystem/wt_l15_adapter.sv
$ARIANE_ROOT/core/cache_subsystem/wt_cache_subsystem.sv
$ARIANE_ROOT/corev_apu/clint/clint.sv
$ARIANE_ROOT/corev_apu/clint/axi_lite_interface.sv
$ARIANE_ROOT/corev_apu/riscv-dbg/debug_rom/debug_rom.sv
$ARIANE_ROOT/corev_apu/riscv-dbg/src/dm_pkg.sv
$ARIANE_ROOT/corev_apu/riscv-dbg/src/dm_csrs.sv
$ARIANE_ROOT/corev_apu/riscv-dbg/src/dm_mem.sv
$ARIANE_ROOT/corev_apu/riscv-dbg/src/dm_top.sv
$ARIANE_ROOT/corev_apu/riscv-dbg/src/dmi_cdc.sv
$ARIANE_ROOT/corev_apu/riscv-dbg/src/dmi_jtag.sv
$ARIANE_ROOT/corev_apu/riscv-dbg/src/dm_sba.sv
$ARIANE_ROOT/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv
$ARIANE_ROOT/corev_apu/openpiton/riscv_peripherals.sv
$ARIANE_ROOT/corev_apu/openpiton/ariane_verilog_wrap.sv
$ARIANE_ROOT/corev_apu/rv_plic/rtl/rv_plic_target.sv
$ARIANE_ROOT/corev_apu/rv_plic/rtl/rv_plic_gateway.sv
$ARIANE_ROOT/corev_apu/rv_plic/rtl/plic_regmap.sv
$ARIANE_ROOT/corev_apu/rv_plic/rtl/plic_top.sv
$ARIANE_ROOT/corev_apu/fpga/src/axi2apb/src/axi2apb_wrap.sv
$ARIANE_ROOT/corev_apu/fpga/src/axi2apb/src/axi2apb.sv
$ARIANE_ROOT/corev_apu/fpga/src/axi2apb/src/axi2apb_64_32.sv
$ARIANE_ROOT/corev_apu/fpga/src/axi_slice/src/axi_w_buffer.sv
$ARIANE_ROOT/corev_apu/fpga/src/axi_slice/src/axi_b_buffer.sv
$ARIANE_ROOT/corev_apu/fpga/src/axi_slice/src/axi_slice_wrap.sv
$ARIANE_ROOT/corev_apu/fpga/src/axi_slice/src/axi_slice.sv
$ARIANE_ROOT/corev_apu/fpga/src/axi_slice/src/axi_single_slice.sv
$ARIANE_ROOT/corev_apu/fpga/src/axi_slice/src/axi_ar_buffer.sv
$ARIANE_ROOT/corev_apu/fpga/src/axi_slice/src/axi_r_buffer.sv
$ARIANE_ROOT/corev_apu/fpga/src/axi_slice/src/axi_aw_buffer.sv
$ARIANE_ROOT/corev_apu/register_interface/src/apb_to_reg.sv
$ARIANE_ROOT/corev_apu/register_interface/src/reg_intf.sv
$ARIANE_ROOT/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
$ARIANE_ROOT/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv
$ARIANE_ROOT/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv
$ARIANE_ROOT/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv
$ARIANE_ROOT/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv
$ARIANE_ROOT/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv
$ARIANE_ROOT/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv
$ARIANE_ROOT/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
$ARIANE_ROOT/vendor/openhwgroup/cvfpu/src/fpnew_cast_multi.sv
$ARIANE_ROOT/vendor/openhwgroup/cvfpu/src/fpnew_classifier.sv
$ARIANE_ROOT/vendor/openhwgroup/cvfpu/src/fpnew_divsqrt_multi.sv
$ARIANE_ROOT/vendor/openhwgroup/cvfpu/src/fpnew_fma_multi.sv
$ARIANE_ROOT/vendor/openhwgroup/cvfpu/src/fpnew_fma.sv
$ARIANE_ROOT/vendor/openhwgroup/cvfpu/src/fpnew_noncomp.sv
$ARIANE_ROOT/vendor/openhwgroup/cvfpu/src/fpnew_opgroup_block.sv
$ARIANE_ROOT/vendor/openhwgroup/cvfpu/src/fpnew_opgroup_fmt_slice.sv
$ARIANE_ROOT/vendor/openhwgroup/cvfpu/src/fpnew_opgroup_multifmt_slice.sv
$ARIANE_ROOT/vendor/openhwgroup/cvfpu/src/fpnew_rounding.sv
$ARIANE_ROOT/vendor/openhwgroup/cvfpu/src/fpnew_top.sv
$ARIANE_ROOT/core/pmp/src/pmp.sv
$ARIANE_ROOT/core/pmp/src/pmp_entry.sv
$ARIANE_ROOT/common/local/util/instr_tracer.sv
$ARIANE_ROOT/common/local/util/instr_tracer_if.sv
$ARIANE_ROOT/core/cvxif_example/cvxif_example_coprocessor.sv
$ARIANE_ROOT/core/cvxif_example/instr_decoder.sv
$ARIANE_ROOT/vendor/pulp-platform/common_cells/src/counter.sv
$ARIANE_ROOT/vendor/pulp-platform/common_cells/src/delta_counter.sv
$ARIANE_ROOT/core/cvxif_fu.sv
6 changes: 2 additions & 4 deletions openpiton/ara_verilog_wrap.sv
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Expand Up @@ -167,14 +167,11 @@ module ara_verilog_wrap
`AXI_TYPEDEF_ALL(ara_axi, axi_addr_t, axi_core_id_t, axi_data_t, axi_strb_t, axi_user_t)
// `AXI_TYPEDEF_ALL(ariane_axi, axi_addr_t, axi_core_id_t, axi_narrow_data_t, axi_narrow_strb_t, axi_user_t)

`AXI_TYPEDEF_ALL(soc_narrow, axi_addr_t, axi_soc_id_t, axi_narrow_data_t, axi_narrow_strb_t,
axi_user_t)
`AXI_TYPEDEF_ALL(soc_narrow, axi_addr_t, axi_soc_id_t, axi_narrow_data_t, axi_narrow_strb_t, axi_user_t)
`AXI_TYPEDEF_ALL(soc_wide, axi_addr_t, axi_soc_id_t, axi_data_t, axi_strb_t, axi_user_t)
`AXI_LITE_TYPEDEF_ALL(soc_narrow_lite, axi_addr_t, axi_narrow_data_t, axi_narrow_strb_t)


system_req_t system_axi_req;
system_resp_t system_axi_resp;
ara_axi_req_t ara_axi_req;
ara_axi_resp_t ara_axi_resp;

Expand Down Expand Up @@ -317,6 +314,7 @@ module ara_verilog_wrap
AxiUserWidth : AxiUserWidth
};


ariane #(
.CVA6Cfg (CVA6Cfg ),
.cvxif_req_t (acc_pkg::accelerator_req_t ),
Expand Down
105 changes: 105 additions & 0 deletions openpiton/ariane.sv
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module ariane import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = cva6_cfg_empty,
parameter type rvfi_instr_t = logic,
parameter type cvxif_req_t = acc_pkg::accelerator_req_t,
parameter type cvxif_resp_t = acc_pkg::accelerator_resp_t,
//
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig,
parameter int unsigned AxiAddrWidth = ariane_axi::AddrWidth,
parameter int unsigned AxiDataWidth = ariane_axi::DataWidth,
parameter int unsigned AxiIdWidth = ariane_axi::IdWidth,
parameter type axi_ar_chan_t = ariane_axi::ar_chan_t,
parameter type axi_aw_chan_t = ariane_axi::aw_chan_t,
parameter type axi_w_chan_t = ariane_axi::w_chan_t,
parameter type noc_req_t = ariane_axi::req_t,
parameter type noc_resp_t = ariane_axi::resp_t
) (
input logic clk_i,
input logic rst_ni,
// Core ID, Cluster ID and boot address are considered more or less static
input logic [riscv::VLEN-1:0] boot_addr_i, // reset boot address
input logic [riscv::XLEN-1:0] hart_id_i, // hart id in a multicore environment (reflected in a CSR)

// Interrupt inputs
input logic [1:0] irq_i, // level sensitive IR lines, mip & sip (async)
input logic ipi_i, // inter-processor interrupts (async)
// Timer facilities
input logic time_irq_i, // timer interrupt in (async)
input logic debug_req_i, // debug request (async)
// RISC-V formal interface port (`rvfi`):
// Can be left open when formal tracing is not needed.
output rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_o,
// Accel interface
output cvxif_req_t cvxif_req_o,
input cvxif_resp_t cvxif_resp_i,

// memory side
output noc_req_t noc_req_o,
input noc_resp_t noc_resp_i
);

// cva6 #(
// .CVA6Cfg ( CVA6Cfg ),
// .rvfi_instr_t ( rvfi_instr_t ),
// .cvxif_req_t (accelerator_req_t ),
// .cvxif_resp_t (accelerator_resp_t),
// .ArianeCfg (ArianeCfg ),
// .axi_ar_chan_t (axi_ar_chan_t),
// .axi_aw_chan_t (axi_aw_chan_t),
// .axi_w_chan_t (axi_w_chan_t ),
// .noc_req_t (noc_req_t ),
// .noc_resp_t (noc_resp_t )
// ) i_cva6 (
// .clk_i ( clk_i ),
// .rst_ni ( rst_ni ),
// .boot_addr_i ( boot_addr_i ),
// .hart_id_i ( hart_id_i ),
// .irq_i ( irq_i ),
// .ipi_i ( ipi_i ),
// .time_irq_i ( time_irq_i ),
// .debug_req_i ( debug_req_i ),
// .rvfi_o ( rvfi_o ),
// .cvxif_req_o ( cvxif_req_o ),
// .cvxif_resp_i ( cvxif_resp_i ),
// .noc_req_o ( noc_req_o ),
// .noc_resp_i ( noc_resp_i )
// );


cva6 #(
.CVA6Cfg (CVA6Cfg ),
.rvfi_instr_t (rvfi_instr_t ),
.cvxif_req_t (cvxif_req_t ),
.cvxif_resp_t (cvxif_resp_t ),
.ArianeCfg (ArianeCfg ),
.axi_ar_chan_t (axi_ar_chan_t ),
.axi_aw_chan_t (axi_aw_chan_t ),
.axi_w_chan_t (axi_w_chan_t ),
.noc_req_t (noc_req_t ),
.noc_resp_t (noc_resp_t )
) i_cva6 (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.boot_addr_i ( boot_addr_i ),
.hart_id_i ( hart_id_i ),
.irq_i ( irq_i ),
.ipi_i ( ipi_i ),
.time_irq_i ( time_irq_i ),
.debug_req_i ( debug_req_i ),
.rvfi_o ( rvfi_o ),
.cvxif_req_o ( cvxif_req_o ),
.cvxif_resp_i ( cvxif_resp_i ),
.noc_req_o ( noc_req_o ),
.noc_resp_i ( noc_resp_i )
);

if (ariane_pkg::CVXIF_PRESENT) begin : gen_example_coprocessor
cvxif_example_coprocessor i_cvxif_coprocessor (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.cvxif_req_i ( cvxif_req ),
.cvxif_resp_o ( cvxif_resp )
);
end

endmodule // ariane

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