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CTS-Avoid level balance buffers overlap. #5819

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CTS-Avoid level balance buffers overlap. #5819

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8977332
avoid overlapping buffer in level balancer
arthurjolo Sep 27, 2024
5a15c55
calng format
arthurjolo Sep 27, 2024
b59b0a5
update direction to where the buffers go
arthurjolo Sep 27, 2024
21bb845
Merge branch 'master' into cts_update_level_balance_placement
arthurjolo Sep 30, 2024
5497643
updtae regression test
arthurjolo Sep 30, 2024
b5187f2
remove unused variable
arthurjolo Oct 4, 2024
b1c7f22
Merge branch 'master' into cts_update_level_balance_placement
arthurjolo Oct 4, 2024
70910ad
add const to varibles
arthurjolo Oct 4, 2024
ef72218
uso correct direction for centroid X
arthurjolo Oct 4, 2024
378a04c
update ok files
arthurjolo Oct 4, 2024
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28 changes: 16 additions & 12 deletions src/cts/src/LevelBalancer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -94,22 +94,26 @@ void LevelBalancer::addBufferLevels(TreeBuilder* builder,
totalX += clockInstObj->getX();
totalY += clockInstObj->getY();
}
const double centroidX = totalX / cluster.size();

const double centroidY = totalY / cluster.size();
const int driverX = prevLevelSubNet->getDriver()->getX();
const int driverY = prevLevelSubNet->getDriver()->getY();
int x = prevLevelSubNet->getDriver()->getX();
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int y = prevLevelSubNet->getDriver()->getY();

int dir = (centroidY - y) / std::abs(centroidY - y);
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Why use the same direction for both x & y? You might be moving away from the centroid in x.

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Yes, I missed that. It was already fixed, thanks.

double height = builder->getBufferHeight() * wireSegmentUnit_ * dir;
double width = builder->getBufferWidth() * wireSegmentUnit_ * dir;

int steps = std::max((int) (std::abs((centroidY - y) / height)), 1);
int buffPerStep = std::ceil((float) bufLevels / (float) steps);
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const


for (unsigned level = 0; level < bufLevels; level++) {
// Add buffer
double x
= (driverX
+ (centroidX - driverX) * (double) (level + 1) / (bufLevels + 1))
/ wireSegmentUnit_;
double y
= (driverY
+ (centroidY - driverY) * (double) (level + 1) / (bufLevels + 1))
/ wireSegmentUnit_;
Point<double> bufferLoc(x, y);
if (level % buffPerStep) {
x = (x + width);
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x += width; is more idiomatic. (likewise y)

} else {
y = (y + height);
}
Point<double> bufferLoc(x / wireSegmentUnit_, y / wireSegmentUnit_);
Point<double> legalBufferLoc
= builder->legalizeOneBuffer(bufferLoc, options_->getSinkBuffer());
ClockInst& levelBuffer = builder->getClock().addClockBuffer(
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96 changes: 48 additions & 48 deletions src/cts/test/balance_levels.defok
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Expand Up @@ -40,54 +40,54 @@ COMPONENTS 413 ;
- clkbuf_4_8__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 141948 26508 ) N ;
- clkbuf_4_9__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 135237 124256 ) N ;
- clkbuf_4_9__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 135237 35368 ) N ;
- clkbuf_level_0_1_1027_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 133484 35513 ) N ;
- clkbuf_level_0_1_10_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 36329 22762 ) N ;
- clkbuf_level_0_1_1130_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 170571 22017 ) N ;
- clkbuf_level_0_1_1233_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 179381 31532 ) N ;
- clkbuf_level_0_1_1336_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 134033 58567 ) N ;
- clkbuf_level_0_1_1439_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 136203 73072 ) N ;
- clkbuf_level_0_1_1542_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 177253 58502 ) N ;
- clkbuf_level_0_1_1645_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 175553 72615 ) N ;
- clkbuf_level_0_1_23_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 27455 30225 ) N ;
- clkbuf_level_0_1_36_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 66780 23660 ) N ;
- clkbuf_level_0_1_49_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 72971 35513 ) N ;
- clkbuf_level_0_1_512_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 30235 60113 ) N ;
- clkbuf_level_0_1_615_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 31658 77098 ) N ;
- clkbuf_level_0_1_718_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 70393 59940 ) N ;
- clkbuf_level_0_1_821_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 68117 75839 ) N ;
- clkbuf_level_0_1_924_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 139675 23660 ) N ;
- clkbuf_level_1_1_1028_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 131732 35659 ) N ;
- clkbuf_level_1_1_1131_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 171668 19585 ) N ;
- clkbuf_level_1_1_11_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 35613 21140 ) N ;
- clkbuf_level_1_1_1234_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 181774 31102 ) N ;
- clkbuf_level_1_1_1337_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 132612 57767 ) N ;
- clkbuf_level_1_1_1440_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 134807 74545 ) N ;
- clkbuf_level_1_1_1543_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 178768 57665 ) N ;
- clkbuf_level_1_1_1646_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 177165 74128 ) N ;
- clkbuf_level_1_1_24_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 24524 29407 ) N ;
- clkbuf_level_1_1_37_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 69053 20813 ) N ;
- clkbuf_level_1_1_410_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 74723 35659 ) N ;
- clkbuf_level_1_1_513_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 28640 59003 ) N ;
- clkbuf_level_1_1_616_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 29589 79586 ) N ;
- clkbuf_level_1_1_719_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 72079 58888 ) N ;
- clkbuf_level_1_1_822_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 69636 77821 ) N ;
- clkbuf_level_1_1_925_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 137402 20813 ) N ;
- clkbuf_level_2_1_1029_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 129980 35805 ) N ;
- clkbuf_level_2_1_1132_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 172765 17153 ) N ;
- clkbuf_level_2_1_1235_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 184167 30671 ) N ;
- clkbuf_level_2_1_12_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 34897 19518 ) N ;
- clkbuf_level_2_1_1338_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 131192 56967 ) N ;
- clkbuf_level_2_1_1441_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 133411 76018 ) N ;
- clkbuf_level_2_1_1544_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 180283 56828 ) N ;
- clkbuf_level_2_1_1647_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 178776 75641 ) N ;
- clkbuf_level_2_1_25_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 21592 28590 ) N ;
- clkbuf_level_2_1_38_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 71326 17965 ) N ;
- clkbuf_level_2_1_411_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 76476 35805 ) N ;
- clkbuf_level_2_1_514_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 27046 57894 ) N ;
- clkbuf_level_2_1_617_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 27520 82074 ) N ;
- clkbuf_level_2_1_720_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 73765 57836 ) N ;
- clkbuf_level_2_1_823_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 71154 79802 ) N ;
- clkbuf_level_2_1_926_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 135130 17965 ) N ;
- clkbuf_level_0_1_1027_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 135237 38168 ) N ;
- clkbuf_level_0_1_10_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 37046 21585 ) N ;
- clkbuf_level_0_1_1130_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 169474 21649 ) N ;
- clkbuf_level_0_1_1233_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 176988 29163 ) N ;
- clkbuf_level_0_1_1336_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 135454 56567 ) N ;
- clkbuf_level_0_1_1439_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 137599 74399 ) N ;
- clkbuf_level_0_1_1542_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 175738 56539 ) N ;
- clkbuf_level_0_1_1645_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 173942 73902 ) N ;
- clkbuf_level_0_1_23_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 30387 28243 ) N ;
- clkbuf_level_0_1_36_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 64508 23708 ) N ;
- clkbuf_level_0_1_49_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 71219 38168 ) N ;
- clkbuf_level_0_1_512_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 31830 58423 ) N ;
- clkbuf_level_0_1_615_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 33728 77410 ) N ;
- clkbuf_level_0_1_718_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 68707 58192 ) N ;
- clkbuf_level_0_1_821_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 66599 76658 ) N ;
- clkbuf_level_0_1_924_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 141948 23708 ) N ;
- clkbuf_level_1_1_1028_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 137137 38168 ) N ;
- clkbuf_level_1_1_1131_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 169474 18849 ) N ;
- clkbuf_level_1_1_11_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 35146 21585 ) N ;
- clkbuf_level_1_1_1234_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 175088 29163 ) N ;
- clkbuf_level_1_1_1337_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 133554 56567 ) N ;
- clkbuf_level_1_1_1440_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 139499 74399 ) N ;
- clkbuf_level_1_1_1543_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 173838 56539 ) N ;
- clkbuf_level_1_1_1646_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 175842 73902 ) N ;
- clkbuf_level_1_1_24_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 28487 28243 ) N ;
- clkbuf_level_1_1_37_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 64508 20908 ) N ;
- clkbuf_level_1_1_410_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 73119 38168 ) N ;
- clkbuf_level_1_1_513_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 29930 58423 ) N ;
- clkbuf_level_1_1_616_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 33728 80210 ) N ;
- clkbuf_level_1_1_719_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 66807 58192 ) N ;
- clkbuf_level_1_1_822_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 68499 76658 ) N ;
- clkbuf_level_1_1_925_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 141948 20908 ) N ;
- clkbuf_level_2_1_1029_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 139037 38168 ) N ;
- clkbuf_level_2_1_1132_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 169474 16049 ) N ;
- clkbuf_level_2_1_1235_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 173188 29163 ) N ;
- clkbuf_level_2_1_12_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 35146 18785 ) N ;
- clkbuf_level_2_1_1338_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 131654 56567 ) N ;
- clkbuf_level_2_1_1441_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 139499 77199 ) N ;
- clkbuf_level_2_1_1544_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 171938 56539 ) N ;
- clkbuf_level_2_1_1647_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 175842 76702 ) N ;
- clkbuf_level_2_1_25_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 26587 28243 ) N ;
- clkbuf_level_2_1_38_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 64508 18108 ) N ;
- clkbuf_level_2_1_411_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 75019 38168 ) N ;
- clkbuf_level_2_1_514_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 28030 58423 ) N ;
- clkbuf_level_2_1_617_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 33728 83010 ) N ;
- clkbuf_level_2_1_720_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 64907 58192 ) N ;
- clkbuf_level_2_1_823_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 68499 79458 ) N ;
- clkbuf_level_2_1_926_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 141948 18108 ) N ;
- clkload0 CLKBUF_X3 + SOURCE TIMING + PLACED ( 37046 24385 ) N ;
- clkload1 CLKBUF_X3 + SOURCE TIMING + PLACED ( 30387 31043 ) N ;
- clkload10 CLKBUF_X3 + SOURCE TIMING + PLACED ( 176988 31963 ) N ;
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2 changes: 1 addition & 1 deletion src/cts/test/balance_levels.ok
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Original file line number Diff line number Diff line change
Expand Up @@ -94,7 +94,7 @@ Fixing from level 2 (parent=0 + current=2) to max 5 for driver clk
[INFO CTS-0098] Clock net "clk"
[INFO CTS-0099] Sinks 151
[INFO CTS-0100] Leaf buffers 0
[INFO CTS-0101] Average sink wire length 125.08 um
[INFO CTS-0101] Average sink wire length 125.43 um
[INFO CTS-0102] Path depth 2 - 5
[INFO CTS-0207] Leaf load cells 30
[INFO CTS-0098] Clock net "CELL\/clk2"
Expand Down
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