Removed STREAMING_SVE and STREAMING_PREDICATE groups and associated l…

…ogic.
UoB-HPC · Dec 5, 2024 · 0af7abc · 0af7abc
1 parent e15f354
commit 0af7abc
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Showing 17 changed files with 95 additions and 406 deletions.
diff --git a/configs/a64fx_SME.yaml b/configs/a64fx_SME.yaml
@@ -95,24 +95,11 @@ Ports:
     Portname: BR
     Instruction-Group-Support:
     - BRANCH
-# Define example SME / SVE Streaming Mode units
+# Define example SME unit
   8:
     Portname: SME
     Instruction-Group-Support:
     - SME
-  9:
-    Portname: PR_S
-    Instruction-Group-Support:
-    - STREAMING_PREDICATE
-  10:
-    Portname: FLA_S
-    Instruction-Group-Support:
-    - STREAMING_SVE
-  11:
-    Portname: FLB_S
-    Instruction-Group-Support:
-    - STREAMING_SVE_SIMPLE
-    - STREAMING_SVE_MUL
 Reservation-Stations:
   0:
     Size: 20
@@ -147,13 +134,6 @@ Reservation-Stations:
     Dispatch-Rate: 1
     Ports:
     - SME
-  6:
-    Size: 40
-    Dispatch-Rate: 3
-    Ports:
-    - FLA_S
-    - FLB_S
-    - PR_S
 Execution-Units:
   0:
     Pipelined: True
@@ -209,24 +189,6 @@ Execution-Units:
     - INT_DIV_OR_SQRT
     - FP_DIV_OR_SQRT
     - SVE_DIV_OR_SQRT
-  9:
-    Pipelined: True
-    Blocking-Groups:
-    - INT_DIV_OR_SQRT
-    - FP_DIV_OR_SQRT
-    - SVE_DIV_OR_SQRT
-  10:
-    Pipelined: True
-    Blocking-Groups:
-    - INT_DIV_OR_SQRT
-    - FP_DIV_OR_SQRT
-    - SVE_DIV_OR_SQRT
-  11:
-    Pipelined: True
-    Blocking-Groups:
-    - INT_DIV_OR_SQRT
-    - FP_DIV_OR_SQRT
-    - SVE_DIV_OR_SQRT
 Latencies:
   0:
     Instruction-Groups: 
@@ -255,11 +217,9 @@ Latencies:
     - SCALAR_SIMPLE
     - VECTOR_SIMPLE_LOGICAL
     - SVE_SIMPLE_LOGICAL
-    - STREAMING_SVE_SIMPLE_LOGICAL
     - SME_SIMPLE_LOGICAL
     - VECTOR_SIMPLE_CMP
     - SVE_SIMPLE_CMP
-    - STREAMING_SVE_SIMPLE_CMP
     - SME_SIMPLE_CMP
     Execution-Latency: 4
     Execution-Throughput: 1
@@ -273,25 +233,21 @@ Latencies:
     - SCALAR_SIMPLE_CVT
     - VECTOR_SIMPLE
     - SVE_SIMPLE
-    - STREAMING_SVE_SIMPLE
     - SME_SIMPLE
     - FP_MUL
     - SVE_MUL
-    - STREAMING_SVE_MUL
     - SME_MUL
     Execution-Latency: 9
     Execution-Throughput: 1
   7:
     Instruction-Groups: 
     - SVE_DIV_OR_SQRT
-    - STREAMING_SVE_DIV_OR_SQRT
     - SME_DIV_OR_SQRT
     Execution-Latency: 98
     Execution-Throughput: 98
   8:
     Instruction-Groups: 
     - PREDICATE
-    - STREAMING_PREDICATE
     Execution-Latency: 3
     Execution-Throughput: 1
   9:
@@ -305,10 +261,8 @@ Latencies:
   10:
     Instruction-Groups: 
     - LOAD_SVE
-    - LOAD_STREAMING_SVE
     - LOAD_SME
     - STORE_ADDRESS_SVE
-    - STORE_ADDRESS_STREAMING_SVE
     - STORE_ADDRESS_SME
     Execution-Latency: 6
     Execution-Throughput: 1

diff --git a/src/include/simeng/arch/aarch64/Instruction.hh b/src/include/simeng/arch/aarch64/Instruction.hh
@@ -370,12 +370,6 @@ class Instruction : public simeng::Instruction {
    * processing this instruction. */
   InstructionException getException() const;
 
-  /** Checks whether the current SVE Streaming Mode status is different to when
-   * this instruction was first decoded, and updates the instruction group
-   * accordingly if required.
-   * Returns TRUE if the group was updated, FALSE otherwise. */
-  bool checkStreamingGroupAndUpdate();
-
  private:
   /** Process the instruction's metadata to determine source/destination
    * registers. */
@@ -457,9 +451,6 @@ class Instruction : public simeng::Instruction {
    * the `InsnType` namespace allowing each bit to represent a unique
    * identifier such as `isLoad` or `isMultiply` etc. */
   uint32_t instructionIdentifier_ = 0;
-
-  /** The instruction group this instruction belongs to. */
-  uint16_t instructionGroup_ = InstructionGroups::NONE;
 };
 
 }  // namespace aarch64

diff --git a/src/include/simeng/arch/aarch64/InstructionGroups.hh b/src/include/simeng/arch/aarch64/InstructionGroups.hh
@@ -98,53 +98,37 @@ const uint16_t LOAD_SVE = 62;
 const uint16_t STORE_ADDRESS_SVE = 63;
 const uint16_t STORE_DATA_SVE = 64;
 const uint16_t STORE_SVE = 65;
-const uint16_t STREAMING_SVE = 66;
-const uint16_t STREAMING_SVE_SIMPLE = 67;
-const uint16_t STREAMING_SVE_SIMPLE_ARTH = 68;
-const uint16_t STREAMING_SVE_SIMPLE_ARTH_NOSHIFT = 69;
-const uint16_t STREAMING_SVE_SIMPLE_LOGICAL = 70;
-const uint16_t STREAMING_SVE_SIMPLE_LOGICAL_NOSHIFT = 71;
-const uint16_t STREAMING_SVE_SIMPLE_CMP = 72;
-const uint16_t STREAMING_SVE_SIMPLE_CVT = 73;
-const uint16_t STREAMING_SVE_MUL = 74;
-const uint16_t STREAMING_SVE_DIV_OR_SQRT = 75;
-const uint16_t LOAD_STREAMING_SVE = 76;
-const uint16_t STORE_ADDRESS_STREAMING_SVE = 77;
-const uint16_t STORE_DATA_STREAMING_SVE = 78;
-const uint16_t STORE_STREAMING_SVE = 79;
-const uint16_t SME = 80;
-const uint16_t SME_SIMPLE = 81;
-const uint16_t SME_SIMPLE_ARTH = 82;
-const uint16_t SME_SIMPLE_ARTH_NOSHIFT = 83;
-const uint16_t SME_SIMPLE_LOGICAL = 84;
-const uint16_t SME_SIMPLE_LOGICAL_NOSHIFT = 85;
-const uint16_t SME_SIMPLE_CMP = 86;
-const uint16_t SME_SIMPLE_CVT = 87;
-const uint16_t SME_MUL = 88;
-const uint16_t SME_DIV_OR_SQRT = 89;
-const uint16_t LOAD_SME = 90;
-const uint16_t STORE_ADDRESS_SME = 91;
-const uint16_t STORE_DATA_SME = 92;
-const uint16_t STORE_SME = 93;
-const uint16_t PREDICATE = 94;
-const uint16_t STREAMING_PREDICATE = 95;
-const uint16_t LOAD = 96;
-const uint16_t STORE_ADDRESS = 97;
-const uint16_t STORE_DATA = 98;
-const uint16_t STORE = 99;
-const uint16_t BRANCH = 100;
-const uint16_t ALL = 101;
-const uint16_t NONE = 102;
+const uint16_t PREDICATE = 66;
+const uint16_t LOAD = 67;
+const uint16_t STORE_ADDRESS = 68;
+const uint16_t STORE_DATA = 69;
+const uint16_t STORE = 70;
+const uint16_t BRANCH = 71;
+const uint16_t SME = 72;
+const uint16_t SME_SIMPLE = 73;
+const uint16_t SME_SIMPLE_ARTH = 74;
+const uint16_t SME_SIMPLE_ARTH_NOSHIFT = 75;
+const uint16_t SME_SIMPLE_LOGICAL = 76;
+const uint16_t SME_SIMPLE_LOGICAL_NOSHIFT = 77;
+const uint16_t SME_SIMPLE_CMP = 78;
+const uint16_t SME_SIMPLE_CVT = 79;
+const uint16_t SME_MUL = 80;
+const uint16_t SME_DIV_OR_SQRT = 81;
+const uint16_t LOAD_SME = 82;
+const uint16_t STORE_ADDRESS_SME = 83;
+const uint16_t STORE_DATA_SME = 84;
+const uint16_t STORE_SME = 85;
+const uint16_t ALL = 86;
+const uint16_t NONE = 87;
 }  // namespace InstructionGroups
 
 /** The number of aarch64 instruction groups. */
-static constexpr uint8_t NUM_GROUPS = 103;
+static constexpr uint8_t NUM_GROUPS = 88;
 
 const std::unordered_map<uint16_t, std::vector<uint16_t>> groupInheritance_ = {
     {InstructionGroups::ALL,
      {InstructionGroups::INT, InstructionGroups::FP, InstructionGroups::SVE,
-      InstructionGroups::STREAMING_SVE, InstructionGroups::SME,
-      InstructionGroups::PREDICATE, InstructionGroups::STREAMING_PREDICATE,
+      InstructionGroups::SME, InstructionGroups::PREDICATE,
       InstructionGroups::LOAD, InstructionGroups::STORE,
       InstructionGroups::BRANCH}},
     {InstructionGroups::INT,
@@ -218,19 +202,6 @@ const std::unordered_map<uint16_t, std::vector<uint16_t>> groupInheritance_ = {
      {InstructionGroups::SVE_SIMPLE_ARTH_NOSHIFT}},
     {InstructionGroups::SVE_SIMPLE_LOGICAL,
      {InstructionGroups::SVE_SIMPLE_LOGICAL_NOSHIFT}},
-    {InstructionGroups::STREAMING_SVE,
-     {InstructionGroups::STREAMING_SVE_SIMPLE,
-      InstructionGroups::STREAMING_SVE_DIV_OR_SQRT,
-      InstructionGroups::STREAMING_SVE_MUL}},
-    {InstructionGroups::STREAMING_SVE_SIMPLE,
-     {InstructionGroups::STREAMING_SVE_SIMPLE_ARTH,
-      InstructionGroups::STREAMING_SVE_SIMPLE_LOGICAL,
-      InstructionGroups::STREAMING_SVE_SIMPLE_CMP,
-      InstructionGroups::STREAMING_SVE_SIMPLE_CVT}},
-    {InstructionGroups::STREAMING_SVE_SIMPLE_ARTH,
-     {InstructionGroups::STREAMING_SVE_SIMPLE_ARTH_NOSHIFT}},
-    {InstructionGroups::STREAMING_SVE_SIMPLE_LOGICAL,
-     {InstructionGroups::STREAMING_SVE_SIMPLE_LOGICAL_NOSHIFT}},
     {InstructionGroups::SME,
      {InstructionGroups::SME_SIMPLE, InstructionGroups::SME_DIV_OR_SQRT,
       InstructionGroups::SME_MUL}},
@@ -244,11 +215,11 @@ const std::unordered_map<uint16_t, std::vector<uint16_t>> groupInheritance_ = {
     {InstructionGroups::LOAD,
      {InstructionGroups::LOAD_INT, InstructionGroups::LOAD_SCALAR,
       InstructionGroups::LOAD_VECTOR, InstructionGroups::LOAD_SVE,
-      InstructionGroups::LOAD_STREAMING_SVE, InstructionGroups::LOAD_SME}},
+      InstructionGroups::LOAD_SME}},
     {InstructionGroups::STORE,
      {InstructionGroups::STORE_INT, InstructionGroups::STORE_SCALAR,
       InstructionGroups::STORE_VECTOR, InstructionGroups::STORE_SVE,
-      InstructionGroups::STORE_STREAMING_SVE, InstructionGroups::STORE_SME}},
+      InstructionGroups::STORE_SME}},
     {InstructionGroups::STORE_INT,
      {InstructionGroups::STORE_ADDRESS_INT, InstructionGroups::STORE_DATA_INT}},
     {InstructionGroups::STORE_SCALAR,
@@ -259,22 +230,17 @@ const std::unordered_map<uint16_t, std::vector<uint16_t>> groupInheritance_ = {
       InstructionGroups::STORE_DATA_VECTOR}},
     {InstructionGroups::STORE_SVE,
      {InstructionGroups::STORE_ADDRESS_SVE, InstructionGroups::STORE_DATA_SVE}},
-    {InstructionGroups::STORE_STREAMING_SVE,
-     {InstructionGroups::STORE_ADDRESS_STREAMING_SVE,
-      InstructionGroups::STORE_DATA_STREAMING_SVE}},
     {InstructionGroups::STORE_SME,
      {InstructionGroups::STORE_ADDRESS_SME, InstructionGroups::STORE_DATA_SME}},
     {InstructionGroups::STORE_ADDRESS,
      {InstructionGroups::STORE_ADDRESS_INT,
       InstructionGroups::STORE_ADDRESS_SCALAR,
       InstructionGroups::STORE_ADDRESS_VECTOR,
       InstructionGroups::STORE_ADDRESS_SVE,
-      InstructionGroups::STORE_ADDRESS_STREAMING_SVE,
       InstructionGroups::STORE_ADDRESS_SME}},
     {InstructionGroups::STORE_DATA,
      {InstructionGroups::STORE_DATA_INT, InstructionGroups::STORE_DATA_SCALAR,
       InstructionGroups::STORE_DATA_VECTOR, InstructionGroups::STORE_DATA_SVE,
-      InstructionGroups::STORE_DATA_STREAMING_SVE,
       InstructionGroups::STORE_DATA_SME}}};
 
 }  // namespace aarch64

diff --git a/src/include/simeng/arch/riscv/Instruction.hh b/src/include/simeng/arch/riscv/Instruction.hh
@@ -252,9 +252,6 @@ class Instruction : public simeng::Instruction {
    * the `InsnType` namespace allowing each bit to represent a unique
    * identifier such as `isLoad` or `isMultiply` etc. */
   uint16_t instructionIdentifier_ = 0;
-
-  /** The instruction group this instruction belongs to. */
-  uint16_t instructionGroup_ = InstructionGroups::NONE;
 };
 
 }  // namespace riscv

diff --git a/src/lib/arch/aarch64/Architecture.cc b/src/lib/arch/aarch64/Architecture.cc
@@ -188,20 +188,6 @@ uint8_t Architecture::predecode(const uint8_t* ptr, uint16_t bytesAvailable,
     newInsn.setExecutionInfo(getExecutionInfo(newInsn));
     // Cache the instruction
     iter = decodeCache_.insert({insn, newInsn}).first;
-  } else {
-    Instruction& cachedInsn = decodeCache_.at(insn);
-    // Check if SVE or Predicate instructions need their group updating due to
-    // SVE Streaming Mode activeness being different from when the instruction
-    // was first decoded.
-    if (cachedInsn.checkStreamingGroupAndUpdate()) {
-      // If the instruction's group has changed then update its execution info.
-      // The newly set group is most likely to be the most accurate, as an
-      // incorrect group allocation is only achieved when an exception/flush is
-      // triggered by changing the SVE Streaming Mode state.
-      cachedInsn.setExecutionInfo(getExecutionInfo(cachedInsn));
-    }
-    // Need to re-set iterator after updating the decodeCache_ structure
-    iter = decodeCache_.find(insn);
   }
 
   // Split instruction into 1 or more defined micro-ops

diff --git a/src/lib/arch/aarch64/Instruction.cc b/src/lib/arch/aarch64/Instruction.cc
@@ -131,7 +131,35 @@ bool Instruction::isLoad() const { return isInstruction(InsnType::isLoad); }
 
 bool Instruction::isBranch() const { return isInstruction(InsnType::isBranch); }
 
-uint16_t Instruction::getGroup() const { return instructionGroup_; }
+uint16_t Instruction::getGroup() const {
+  // Use identifiers to decide instruction group
+  // Set base
+  uint16_t base = InstructionGroups::INT;
+  if (isInstruction(InsnType::isScalarData))
+    base = InstructionGroups::SCALAR;
+  else if (isInstruction(InsnType::isVectorData))
+    base = InstructionGroups::VECTOR;
+  else if (isInstruction(InsnType::isSVEData))
+    base = InstructionGroups::SVE;
+  else if (isInstruction(InsnType::isSMEData))
+    base = InstructionGroups::SME;
+
+  if (isInstruction(InsnType::isLoad)) return base + 10;
+  if (isInstruction(InsnType::isStoreAddress)) return base + 11;
+  if (isInstruction(InsnType::isStoreData)) return base + 12;
+  if (isInstruction(InsnType::isBranch)) return InstructionGroups::BRANCH;
+  if (isInstruction(InsnType::isPredicate)) return InstructionGroups::PREDICATE;
+  if (isInstruction(InsnType::isDivideOrSqrt)) return base + 9;
+  if (isInstruction(InsnType::isMultiply)) return base + 8;
+  if (isInstruction(InsnType::isConvert)) return base + 7;
+  if (isInstruction(InsnType::isCompare)) return base + 6;
+  if (isInstruction(InsnType::isLogical)) {
+    if (isInstruction(InsnType::isShift)) return base + 4;
+    return base + 5;
+  }
+  if (isInstruction(InsnType::isShift)) return base + 2;
+  return base + 3;  // Default return is {Data type}_SIMPLE_ARTH
+}
 
 bool Instruction::canExecute() const { return (sourceOperandsPending_ == 0); }
 
@@ -164,33 +192,6 @@ const Architecture& Instruction::getArchitecture() const {
 
 InstructionException Instruction::getException() const { return exception_; }
 
-bool Instruction::checkStreamingGroupAndUpdate() {
-  // Only instruction groups that depend on SVE Streaming Mode are SVE and
-  // PREDICATE
-  const uint16_t currentGroup = instructionGroup_;
-  const bool smEnabled = architecture_.isStreamingModeEnabled();
-  if (isInstruction(InsnType::isPredicate)) {
-    // Decide on predicate group based on whether SVE Streaming Mode is enabled.
-    instructionGroup_ = smEnabled ? InstructionGroups::STREAMING_PREDICATE
-                                  : InstructionGroups::PREDICATE;
-  } else if (isInstruction(InsnType::isSVEData)) {
-    assert(((instructionGroup_ >= InstructionGroups::SVE &&
-             instructionGroup_ <= InstructionGroups::STORE_SVE) ||
-            (instructionGroup_ >= InstructionGroups::STREAMING_SVE &&
-             instructionGroup_ <= InstructionGroups::STORE_STREAMING_SVE)) &&
-           "Invalid instruction group for SVE instruction.");
-    // Get instruction group offset.
-    instructionGroup_ -= (instructionGroup_ >= InstructionGroups::STREAMING_SVE)
-                             ? InstructionGroups::STREAMING_SVE
-                             : InstructionGroups::SVE;
-    // Add instruction group base depending on whether SVE Streaming Mode is
-    // enabled.
-    instructionGroup_ +=
-        smEnabled ? InstructionGroups::STREAMING_SVE : InstructionGroups::SVE;
-  }
-  return (currentGroup != instructionGroup_);
-}
-
 }  // namespace aarch64
 }  // namespace arch
 }  // namespace simeng