Attended PR comments.

CMakeLists.txt

@@ -157,8 +157,7 @@ if(SIMENG_ENABLE_TESTS)
       # Print message containing if the full test suite will run
     if (${LLVM_PACKAGE_VERSION} VERSION_LESS "14.0")
       message(STATUS "LLVM version does not support AArch64 extensions SVE2, SVE2.1, SME, or SME2. Related tests will fail.")
-    endif()
-    if (${LLVM_PACKAGE_VERSION} VERSION_LESS "18.0")
+    elseif (${LLVM_PACKAGE_VERSION} VERSION_LESS "18.0")
       message(STATUS "LLVM version does not support AArch64 extensions SME2 or SVE2.1. Related test will fail.")
     endif()
 

src/include/simeng/arch/aarch64/Instruction.hh

@@ -306,9 +306,10 @@ std::vector<std::array<uint64_t, 4>> predAsCounterToMasks(
     for (int i = 0; i < elemsPerVec; i++) {
       // Move bit to next position based on element type
       uint64_t shifted_active = 1ull << ((i % (64 / sizeof(T))) * sizeof(T));
-      // If invert = 1, predElemCount dictates number of initial inactive
-      // elements.
-      // If invert = 0, it is number of initial active elements.
+      // If invert = True (invert bit = 1), predElemCount dictates number of
+      // initial inactive elements.
+      // If invert = False (invert bit = 0), it indicates the number of initial
+      // active elements.
       if ((r * elemsPerVec) + i < predElemCount) {
         out[r][i / (64 / sizeof(T))] |= (invert) ? 0 : shifted_active;
       } else {

src/include/simeng/arch/aarch64/helpers/sve.hh

@@ -626,7 +626,7 @@ std::enable_if_t<std::is_floating_point_v<T>, RegisterValue> sveFDivPredicated(
   return {out, 256};
 }
 
-/** Helpfer function for SVE instructions with the format `faddv rd, pg, zn.
+/** Helper function for SVE instructions with the format `faddv rd, pg, zn.
  * D represents the source vector element type and the destination scalar
  * register type (i.e. for zn.s and sd, D = float).
  * Returns correctly formatted RegisterValue. */