Attended PR comments.

CMakeLists.txt

@@ -72,7 +72,7 @@ set(CMAKE_MACOSX_RPATH 1)
 set(CMAKE_POSITION_INDEPENDENT_CODE ON)
 
 # Create variable to enable additional compiler warnings for SimEng targets only
-set(SIMENG_COMPILE_OPTIONS -Wall -pedantic) #-Wextra
+set(SIMENG_COMPILE_OPTIONS -Wall -pedantic -Werror) #-Wextra
 
 # Disable RTTI for all targets
 add_compile_options($<$<COMPILE_LANGUAGE:CXX>:-fno-rtti>)

configs/a64fx_SME.yaml

@@ -62,12 +62,7 @@ Ports:
     Instruction-Group-Support:
     - INT_SIMPLE
     - INT_MUL
-    - STORE_DATA_INT
-    - STORE_DATA_SCALAR
-    - STORE_DATA_VECTOR
-    - STORE_DATA_SVE
-    - STORE_DATA_STREAMING_SVE
-    - STORE_DATA_SME
+    - STORE_DATA
   3:
     Portname: FLB
     Instruction-Group-Support:
@@ -83,36 +78,16 @@ Ports:
   5:
     Portname: EAGA
     Instruction-Group-Support: 
-    - LOAD_INT
-    - LOAD_SCALAR
-    - LOAD_VECTOR
-    - LOAD_SVE
-    - LOAD_STREAMING_SVE
-    - LOAD_SME
-    - STORE_ADDRESS_INT
-    - STORE_ADDRESS_SCALAR
-    - STORE_ADDRESS_VECTOR
-    - STORE_ADDRESS_SVE
-    - STORE_ADDRESS_STREAMING_SVE
-    - STORE_ADDRESS_SME
+    - LOAD
+    - STORE_ADDRESS
     - INT_SIMPLE_ARTH_NOSHIFT
     - INT_SIMPLE_LOGICAL_NOSHIFT
     - INT_SIMPLE_CMP
   6:
     Portname: EAGB
     Instruction-Group-Support:
-    - LOAD_INT
-    - LOAD_SCALAR
-    - LOAD_VECTOR
-    - LOAD_SVE
-    - LOAD_STREAMING_SVE
-    - LOAD_SME
-    - STORE_ADDRESS_INT
-    - STORE_ADDRESS_SCALAR
-    - STORE_ADDRESS_VECTOR
-    - STORE_ADDRESS_SVE
-    - STORE_ADDRESS_STREAMING_SVE
-    - STORE_ADDRESS_SME
+    - LOAD
+    - STORE_ADDRESS
     - INT_SIMPLE_ARTH_NOSHIFT
     - INT_SIMPLE_LOGICAL_NOSHIFT
     - INT_SIMPLE_CMP

src/include/simeng/Register.hh

@@ -1,6 +1,5 @@
 #pragma once
 #include <cstdint>
-#include <iostream>
 
 namespace simeng {
 

src/include/simeng/arch/aarch64/Architecture.hh

@@ -74,7 +74,7 @@ class Architecture : public arch::Architecture {
   bool isStreamingModeEnabled() const;
 
   /** Returns if the SME ZA Register is enabled. */
-  bool isZA_RegisterEnabled() const;
+  bool isZARegisterEnabled() const;
 
   /** Update the value of SVCRval_. */
   void setSVCRval(const uint64_t newVal) const;

src/include/simeng/arch/aarch64/Instruction.hh

@@ -374,7 +374,7 @@ class Instruction : public simeng::Instruction {
    * this instruction was first decoded, and updates the instruction group
    * accordingly if required.
    * Returns TRUE if the group was updated, FALSE otherwise. */
-  bool checkStreamingGroup();
+  bool checkStreamingGroupAndUpdate();
 
  private:
   /** Process the instruction's metadata to determine source/destination

src/include/simeng/arch/aarch64/InstructionGroups.hh

@@ -4,7 +4,33 @@ namespace simeng {
 namespace arch {
 namespace aarch64 {
 
-/** The IDs of the instruction groups for AArch64 instructions. */
+/** The IDs of the instruction groups for AArch64 instructions.
+ * Each new group must contain 14 entries to ensure correct group assignment and
+ * general functionality.
+ * Their order must be as follows:
+ *  - BASE
+ *  - BASE_SIMPLE
+ *  - BASE_SIMPLE_ARTH
+ *  - BASE_SIMPLE_ARTH_NOSHIFT
+ *  - BASE_SIMPLE_LOGICAL
+ *  - BASE_SIMPLE_LOGICAL_NOSHIFT
+ *  - BASE_SIMPLE_CMP
+ *  - BASE_SIMPLE_CVT
+ *  - BASE_MUL
+ *  - BASE_DIV_OR_SQRT
+ *  - LOAD_BASE
+ *  - STORE_ADDRESS_BASE
+ *  - STORE_DATA_BASE
+ *  - STORE_BASE
+ *
+ * An exception to the above is "Parent" groups which do not require the LOAD_*
+ * or STORE_* groups.
+ * "Parent" groups allow for easier grouping of similar groups that may have
+ * identical execution latencies, ports, etc. For example, FP is the parent
+ * group of SCALAR and VECTOR.
+ * In simulation, an instruction's allocated group will never be a "Parent"
+ * group; they are only used to simplify config file creation and management.
+ */
 namespace InstructionGroups {
 const uint16_t INT = 0;
 const uint16_t INT_SIMPLE = 1;

src/lib/arch/aarch64/Architecture.cc

@@ -193,7 +193,7 @@ uint8_t Architecture::predecode(const uint8_t* ptr, uint16_t bytesAvailable,
     // Check if SVE or Predicate instructions need their group updating due to
     // SVE Streaming Mode activeness being different from when the instruction
     // was first decoded.
-    if (cachedInsn.checkStreamingGroup()) {
+    if (cachedInsn.checkStreamingGroupAndUpdate()) {
       // If the instruction's group has changed then update its execution info.
       // The newly set group is most likely to be the most accurate, as an
       // incorrect group allocation is only achieved when an exception/flush is
@@ -299,7 +299,7 @@ void Architecture::setSVCRval(const uint64_t newVal) const {
 bool Architecture::isStreamingModeEnabled() const { return SVCRval_ & 1; }
 
 // 1st bit of SVCR register determines if ZA register is enabled.
-bool Architecture::isZA_RegisterEnabled() const { return SVCRval_ & 2; }
+bool Architecture::isZARegisterEnabled() const { return SVCRval_ & 2; }
 
 }  // namespace aarch64
 }  // namespace arch

src/lib/arch/aarch64/Instruction.cc

@@ -164,7 +164,7 @@ const Architecture& Instruction::getArchitecture() const {
 
 InstructionException Instruction::getException() const { return exception_; }
 
-bool Instruction::checkStreamingGroup() {
+bool Instruction::checkStreamingGroupAndUpdate() {
   // Only instruction groups that depend on SVE Streaming Mode are SVE and
   // PREDICATE
   const uint16_t currentGroup = instructionGroup_;