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Fixed issues arising from merge conflicts on Capstone Update branch. …
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…Updated comment for infinite loop detector
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@JosephMoore25
JosephMoore25 committed Dec 20, 2024
1 parent 6da7f5c commit c9f708b
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Showing 6 changed files with 70 additions and 23 deletions.
14 changes: 7 additions & 7 deletions src/include/simeng/arch/aarch64/helpers/sve.hh
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Original file line number Diff line number Diff line change
Expand Up @@ -1120,9 +1120,9 @@ RegisterValue sveLastBSimdScalar(srcValContainer& sourceValues,
template <typename T>
RegisterValue sveCLastBSimdScalar(srcValContainer& sourceValues,
const uint16_t VL_bits) {
const uint64_t* p = sourceValues[1].getAsVector<uint64_t>();
const T* m = sourceValues[2].getAsVector<T>();
const T* n = sourceValues[3].getAsVector<T>();
const uint64_t* p = sourceValues[0].getAsVector<uint64_t>();
const T* m = sourceValues[1].getAsVector<T>();
const T* n = sourceValues[2].getAsVector<T>();

const uint16_t partition_num = VL_bits / (sizeof(T) * 8);
T out;
Expand Down Expand Up @@ -1510,8 +1510,8 @@ std::array<uint64_t, 4> svePsel(
std::tuple<std::array<uint64_t, 4>, uint8_t> svePfirst(
srcValContainer& sourceValues, const uint16_t VL_bits) {
const uint16_t partition_num = VL_bits / 8;
const uint64_t* p = sourceValues[1].getAsVector<uint64_t>();
const uint64_t* dn = sourceValues[2].getAsVector<uint64_t>();
const uint64_t* p = sourceValues[0].getAsVector<uint64_t>();
const uint64_t* dn = sourceValues[1].getAsVector<uint64_t>();
// Set destination d as source n to copy all false lanes and the active lanes
// beyond the first
std::array<uint64_t, 4> out = {dn[0], dn[1], dn[2], dn[3]};
Expand All @@ -1535,8 +1535,8 @@ std::tuple<std::array<uint64_t, 4>, uint8_t> svePnext(
const simeng::arch::aarch64::InstructionMetadata& metadata,
const uint16_t VL_bits) {
const uint16_t partition_num = VL_bits / (sizeof(T) * 8);
const uint64_t* p = sourceValues[1].getAsVector<uint64_t>();
const uint64_t* dn = sourceValues[2].getAsVector<uint64_t>();
const uint64_t* p = sourceValues[0].getAsVector<uint64_t>();
const uint64_t* dn = sourceValues[1].getAsVector<uint64_t>();
// Set destination elements to 0
std::array<uint64_t, 4> out = {0, 0, 0, 0};

Expand Down
4 changes: 4 additions & 0 deletions src/include/simeng/pipeline/ReorderBuffer.hh
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Original file line number Diff line number Diff line change
Expand Up @@ -129,6 +129,10 @@ class ReorderBuffer {
* the ROB */
uint64_t robHeadRepeatCounter_ = 0;

/** A limit for the counter of how long an instruction can be stuck at the
* head of the ROB before SimEng exits with an exception. */
uint64_t robHeadRepeatLimit_ = 10000000;

/** The sequence ID of the youngest instruction that should remain after the
* current flush. */
uint64_t flushAfter_;
Expand Down
55 changes: 47 additions & 8 deletions src/lib/arch/aarch64/InstructionMetadata.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -89,14 +89,6 @@ InstructionMetadata::InstructionMetadata(const cs_insn& insn)
}
case Opcode::AArch64_SMAX_ZI_B:
[[fallthrough]];
case Opcode::AArch64_FTSMUL_ZZZ_D:
[[fallthrough]];
case Opcode::AArch64_FTSMUL_ZZZ_S:
[[fallthrough]];
case Opcode::AArch64_FTSSEL_ZZZ_D:
[[fallthrough]];
case Opcode::AArch64_FTSSEL_ZZZ_S:
[[fallthrough]];
case Opcode::AArch64_SMAX_ZI_D:
[[fallthrough]];
case Opcode::AArch64_SMAX_ZI_H:
Expand All @@ -108,6 +100,14 @@ InstructionMetadata::InstructionMetadata(const cs_insn& insn)
operands[0].access = CS_AC_WRITE;
operands[1].access = CS_AC_READ;
break;
case Opcode::AArch64_FTSMUL_ZZZ_D:
[[fallthrough]];
case Opcode::AArch64_FTSMUL_ZZZ_S:
[[fallthrough]];
case Opcode::AArch64_FTSSEL_ZZZ_D:
[[fallthrough]];
case Opcode::AArch64_FTSSEL_ZZZ_S:
[[fallthrough]];
case Opcode::AArch64_FSUB_ZPmI_D:
[[fallthrough]];
case Opcode::AArch64_FSUB_ZPmI_H:
Expand All @@ -131,6 +131,41 @@ InstructionMetadata::InstructionMetadata(const cs_insn& insn)
operands[2].access = CS_AC_READ;
break;
}
case Opcode::AArch64_FTMAD_ZZI_D:
[[fallthrough]];
case Opcode::AArch64_FTMAD_ZZI_S: {
// Incorrect access types
operands[0].access = CS_AC_READ | CS_AC_WRITE;
operands[1].access = CS_AC_READ;
operands[2].access = CS_AC_READ;
break;
}
case Opcode::AArch64_PFIRST_B:
[[fallthrough]];
case Opcode::AArch64_PNEXT_D:
[[fallthrough]];
case Opcode::AArch64_PNEXT_S:
[[fallthrough]];
case Opcode::AArch64_PNEXT_H:
[[fallthrough]];
case Opcode::AArch64_PNEXT_B: {
// Incorrect access types
operands[0].access = CS_AC_WRITE;
operands[1].access = CS_AC_READ;
operands[2].access = CS_AC_READ;
// Doesn't identify implicit NZCV destination
implicitDestinationCount = 1;
implicitDestinations[0] = AARCH64_REG_NZCV;
break;
}
case Opcode::AArch64_CLASTB_VPZ_D:
[[fallthrough]];
case Opcode::AArch64_CLASTB_VPZ_S:
[[fallthrough]];
case Opcode::AArch64_CLASTB_VPZ_H:
[[fallthrough]];
case Opcode::AArch64_CLASTB_VPZ_B:
[[fallthrough]];
case Opcode::AArch64_AND_ZPmZ_D: // Example bytecode - 4901da04
[[fallthrough]];
case Opcode::AArch64_AND_ZPmZ_H:
Expand Down Expand Up @@ -163,6 +198,10 @@ InstructionMetadata::InstructionMetadata(const cs_insn& insn)
[[fallthrough]];
case Opcode::AArch64_SMAX_ZPmZ_S: // Example bytecode - 01008804
[[fallthrough]];
case Opcode::AArch64_SPLICE_ZPZ_D:
[[fallthrough]];
case Opcode::AArch64_SPLICE_ZPZ_S:
[[fallthrough]];
case Opcode::AArch64_MUL_ZPmZ_B: // Example bytecode - 40001004
[[fallthrough]];
case Opcode::AArch64_MUL_ZPmZ_D:
Expand Down
7 changes: 4 additions & 3 deletions src/lib/arch/aarch64/Instruction_decode.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -499,9 +499,10 @@ void Instruction::decode() {

// Check first operand access to determine if it's a load or store
if (metadata_.operands[0].access & CS_AC_WRITE) {
if (metadata_.id == ARM64_INS_STXR || metadata_.id == ARM64_INS_STLXR ||
metadata_.id == ARM64_INS_STLXRB ||
metadata_.id == ARM64_INS_STLXRH) {
if (metadata_.id == AARCH64_INS_STXR ||
metadata_.id == AARCH64_INS_STLXR ||
metadata_.id == AARCH64_INS_STLXRB ||
metadata_.id == AARCH64_INS_STLXRH) {
// Exceptions to this is load condition are exclusive store with a
// success flag as first operand
if (microOpcode_ != MicroOpcode::STR_DATA) {
Expand Down
11 changes: 7 additions & 4 deletions src/lib/pipeline/ReorderBuffer.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -86,17 +86,20 @@ unsigned int ReorderBuffer::commit(uint64_t maxCommitSize) {
// If an instruction has been stuck at the head of the rob for
// sufficiently long, assume an error in SimEng has occured.
robHeadRepeatCounter_++;
if (robHeadRepeatCounter_ > 10000000) {
if (robHeadRepeatCounter_ > robHeadRepeatLimit_) {
std::cerr << "[SimEng:ReorderBuffer] Instruction stuck unable to "
"commit at the head of ROB for a very long time at "
"commit at the head of ROB for 10,000,000 cycles at "
"instruction address 0x"
<< std::hex << uop->getInstructionAddress() << std::dec
<< " (MicroOp Index: " << uop->getMicroOpIndex()
<< "). This is unexpected behaviour for most valid core "
"configurations, though may arise in designs with very "
"high latencies or bottlenecks. If this is not the case, "
"please try re-running. Please raise an issue on GitHub "
"if the problem persists."
"please try re-running. If this may be expected, you can "
"increase this limit in "
"`SimEng/src/include/pipeline/ReorderBuffer.hh` under the "
"variable `robHeadRepeatLimit_`. Please raise "
"an issue on GitHub if the problem persists."
<< std::endl;
exit(1);
}
Expand Down
2 changes: 1 addition & 1 deletion test/regression/aarch64/instructions/sve.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -5017,7 +5017,7 @@ TEST_P(InstSve, ftsmul) {
144.0f, 12.25f},
VL / 16));

EXPECT_GROUP(R"(ftsmul z3.s, z1.s, z0.s)", SVE_MUL);
EXPECT_GROUP(R"(ftsmul z3.s, z1.s, z0.s)", SVE_SIMPLE_ARTH_NOSHIFT);
}

TEST_P(InstSve, ftssel) {
Expand Down

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