Tage

configs/a64fx.yaml

@@ -29,10 +29,15 @@ Queue-Sizes:
   Load: 40
   Store: 24
 Branch-Predictor:
-  Type: "Perceptron"
+  Type: "Tage"
   BTB-Tag-Bits: 11
+  Saturating-Count-Bits: 2
   Global-History-Length: 19
   RAS-entries: 8
+  Fallback-Static-Predictor: "Always-Taken"
+  Tage-Table-Bits: 12
+  Num-Tage-Tables: 6
+  Tag-Length: 8
 L1-Data-Memory:
   Interface-Type: Fixed
 L1-Instruction-Memory:

docs/sphinx/developer/components/branchPred.rst

@@ -21,7 +21,6 @@ The state of the branch predictor when ``predict`` is called on a branch is stor
 
 Generic Predictor
 -----------------
-
 The algorithm(s) held within a ``BranchPredictor`` class instance can be model-specific, however, SimEng provides a ``GenericPredictor`` which contains the following logic.
 
 Global History
@@ -53,4 +52,20 @@ Branch Target Buffer (BTB)
     If the supplied branch type is ``Unconditional``, then the predicted direction is overridden to be taken. If the supplied branch type is ``Conditional`` and the predicted direction is not taken, then the predicted target is overridden to be the next sequential instruction.
 
 Return Address Stack (RAS)
-    Identified through the supplied branch type, Return instructions pop values off of the RAS to get their branch target whilst Branch-and-Link instructions push values onto the RAS, for later use by the Branch-and-Link instruction's corresponding Return instruction.
+    Identified through the supplied branch type, Return instructions pop values off of the RAS to get their branch target whilst Branch-and-Link instructions push values onto the RAS, for later use by the Branch-and-Link instruction's corresponding Return instruction.
+
+TAGE Predictor
+--------------------
+The ``TagePredictor`` is a TAGE predictor of the type described in https://inria.hal.science/hal-03408381/document.  Unlike ``GenericPredictor`` and ``PerceptronPredictor``, this predictor uses a series of prediction tables, each of which uses an increasing global history size.  E.g., the default prediction table will be indexed by the address itself, then the following tables will use global histories of length 2, 4, 8, 16, ....
+
+Tagged prediction tables
+    The prediction returned from this branch predictor will be that determined by the table with the largest global history that has an entry corresponding to the given branch.  To determine whether or not a table entry corresponds to the present branch or not, a hash is made from the branch's address and the global history.  Each table entry has a usefulness counter which is updated when the prediction differs from the next-best prediction.  On incorrect prediction, if possible, replace a non-useful entry in a table with more global history.
+
+Default prediction table
+    In addition to the tagged tables, there is a non-tagged default prediction table that is used as a fall-back in the event that none of the tagged tables have an entry corresponding to a given branch.  This table is much like the BTB in the ``GenericPredictor``, except that the index is determined from the truncated address only (i.e., it does not depend on the global history at all).
+
+Global History
+    To accomodate larger numbers of tagged tables, global histories of greater than 64 bits are needed.  Therefore, ``TagePredictor`` incorporates a new ``BranchHistory`` structure that allows global histories of unlimited size to be kept and accessed.
+
+Return Address Stack (RAS)
+    Identified through the supplied branch type, Return instructions pop values off of the RAS to get their branch target whilst Branch-and-Link instructions push values onto the RAS, for later use by the Branch-and-Link instruction's corresponding Return instruction.

docs/sphinx/user/configuring_simeng.rst

@@ -149,13 +149,13 @@ The Branch-Prediction section contains those options to parameterise the branch
 The current options include:
 
 Type
-    The type of branch predictor that is used, the options are ``Generic``, and ``Perceptron``.  Both types of predictor use a branch target buffer with each entry containing a direction prediction mechanism and a target address.  The direction predictor used in ``Generic`` is a saturating counter, and in ``Perceptron`` it is a perceptron.
+    The type of branch predictor that is used, the options are ``Generic``, ``Perceptron``, and ``Tage``.  Each of these types of predictor use prediction tables with each entry containing a direction prediction mechanism and a target address.  The direction predictor used in ``Generic`` and ``TAGE`` is a saturating counter, and in ``Perceptron`` it is a perceptron.  ``TAGE`` also uses a series of further, tagged prediction tables to provide predictions informed by greater branch histories.
 
 BTB-Tag-Bits
     The number of bits used to index the entries in the Branch Target Buffer (BTB). The number of entries in the BTB is obtained from the calculation: 1 << ``bits``. For example, a ``bits`` value of 12 would result in a BTB with 4096 entries.
 
 Saturating-Count-Bits
-    Only needed for a ``Generic`` predictor.  The number of bits used in the saturating counter value.
+    Only needed for ``Generic`` and ``Tage`` predictors.  The number of bits used in the saturating counter value.
 
 Global-History-Length
     The number of bits used to record the global history of branch directions. Each bit represents one branch direction.  For ``PerceptronPredictor``, this dictates the size of the perceptrons (with each perceptron having Global-History-Length + 1 weights).
@@ -164,7 +164,16 @@ RAS-entries
     The number of entries in the Return Address Stack (RAS).
 
 Fallback-Static-Predictor
-    Only needed for a ``Generic`` predictor.  The static predictor used when no dynamic prediction is available. The options are either ``"Always-Taken"`` or ``"Always-Not-Taken"``.
+    Only needed for ``Generic`` and ``Tage`` predictors.  The static predictor used when no dynamic prediction is available. The options are either ``"Always-Taken"`` or ``"Always-Not-Taken"``.
+
+Tage-Table-Bits
+    Only needed for a ``Tage`` predictor.  The number of bits used to index entries in the tagged tables.  The number of entries in each of the tagged tables is obtained from the calculation: 1 << ``bits``.  For examples, a ``bits`` value of 12 would result in tagged tables with 4096 entries.
+
+Num-Tage-Tables
+    Only needed for a ``Tage`` predictor.  The number of tagged tables used by the predictor, in addition to a default prediction table (i.e., the BTB).  Therefore, a value of 3 for ``Num-Tage-Tables`` would result in four total prediction tables: one BTB and three tagged tables.  If no tagged tables are desired, it is recommended to use the ``GenericPredictor`` instead.
+
+Tage-Length
+    Only needed for a ``Tage`` predictor.  The number of bits used to tage the entries of the tagged tables.
 
 .. _l1dcnf:
 

src/include/simeng/CoreInstance.hh

@@ -11,6 +11,7 @@
 #include "simeng/branchpredictors/AlwaysNotTakenPredictor.hh"
 #include "simeng/branchpredictors/GenericPredictor.hh"
 #include "simeng/branchpredictors/PerceptronPredictor.hh"
+#include "simeng/branchpredictors/TagePredictor.hh"
 #include "simeng/config/SimInfo.hh"
 #include "simeng/kernel/Linux.hh"
 #include "simeng/memory/FixedLatencyMemoryInterface.hh"

src/include/simeng/Instruction.hh

@@ -29,7 +29,7 @@ struct ExecutionInfo {
  * Each supported ISA should provide a derived implementation of this class. */
 class Instruction {
  public:
-  virtual ~Instruction(){};
+  virtual ~Instruction() {};
 
   /** Retrieve the source registers this instruction reads. */
   virtual const span<Register> getSourceRegisters() const = 0;

src/include/simeng/arch/ArchInfo.hh

@@ -12,7 +12,7 @@ namespace arch {
 /** A class to hold and generate architecture specific configuration options. */
 class ArchInfo {
  public:
-  virtual ~ArchInfo(){};
+  virtual ~ArchInfo() {};
 
   /** Get the set of system register enums currently supported. */
   virtual const std::vector<uint64_t>& getSysRegEnums() const = 0;

src/include/simeng/arch/Architecture.hh

@@ -30,7 +30,7 @@ struct ExceptionResult {
  * cycle until complete. */
 class ExceptionHandler {
  public:
-  virtual ~ExceptionHandler(){};
+  virtual ~ExceptionHandler() {};
   /** Tick the exception handler to progress handling of the exception. Should
    * return `false` if the exception requires further handling, or `true` once
    * complete. */
@@ -46,7 +46,7 @@ class Architecture {
  public:
   Architecture(kernel::Linux& kernel) : linux_(kernel) {}
 
-  virtual ~Architecture(){};
+  virtual ~Architecture() {};
 
   /** Attempt to pre-decode from `bytesAvailable` bytes of instruction memory.
    * Writes into the supplied macro-op vector, and returns the number of bytes

src/include/simeng/branchpredictors/AlwaysNotTakenPredictor.hh

@@ -27,4 +27,4 @@ class AlwaysNotTakenPredictor : public BranchPredictor {
  private:
 };
 
-}  // namespace simeng
+}  // namespace simeng

src/include/simeng/branchpredictors/BranchHistory.hh

@@ -0,0 +1,114 @@
+#pragma once
+
+#include <cstdint>
+#include <memory>
+
+namespace simeng {
+/** A class for storing a branch history.  Needed for cases where a branch
+ * history of more than 64 bits is required.  This class makes it easier to
+ * access and manipulate large branch histories, as are needed in
+ * sophisticated branch predictors.
+ *
+ * The bits of the branch history are stored in a vector of uint64_t values,
+ * and their access/manipulation is facilitated by the public functions. */
+
+class BranchHistory {
+ public:
+  BranchHistory(uint64_t size) : size_(size) {
+    history_ = std::make_unique<uint64_t[]>(size_);
+  }
+
+  ~BranchHistory() {};
+
+  /** Returns the 'numBits' most recent bits of the branch history.  Maximum
+   * number of bits returnable is 64 to allow it to be provided in a 64-bit
+   * integer. */
+  uint64_t getHistory(uint8_t numBits) {
+    assert(numBits <= 64 && "Cannot get more than 64 bits without rolling");
+    assert(numBits <= size_ &&
+           "Cannot get more bits of branch history than "
+           "the size of the history");
+    return (history_[0] & ((1ull << numBits) - 1));
+  }
+
+  /** Returns 'numBits' of the global history folded over on itself to get a
+   * value of size 'length'.  The global history is folded by taking an
+   * XOR hash with the overflowing bits to get an output of 'length' bits. */
+  uint64_t getFolded(uint8_t numBits, uint8_t length) {
+    assert(numBits <= size_ &&
+           "Cannot get more bits of branch history than "
+           "the size of the history");
+    uint64_t output = 0;
+
+    uint64_t startIndex = 0;
+    uint64_t endIndex = numBits - 1;
+
+    while (startIndex <= numBits) {
+      output ^= ((history_[startIndex / 64] >> startIndex) &
+                 ((1ull << (numBits - startIndex)) - 1));
+
+      // Check to see if a second uint64_t value will need to be accessed
+      if ((startIndex / 64) == (endIndex / 64)) {
+        uint8_t leftOverBits = endIndex % 64;
+        output ^= (history_[endIndex / 64] << (numBits - leftOverBits));
+      }
+      startIndex += length;
+      endIndex += length;
+    }
+
+    // Trim the output to the desired size
+    output &= (1 << length) - 1;
+    return output;
+  }
+
+  /** Adds a branch outcome ('isTaken') to the global history */
+  void addHistory(bool isTaken) {
+    for (int8_t i = size_ / 64; i >= 0; i--) {
+      history_[i] <<= 1;
+      if (i == 0) {
+        history_[i] |= ((isTaken) ? 1 : 0);
+      } else {
+        history_[i] |= (((history_[i - 1] & (1ull << 63)) > 0) ? 1 : 0);
+      }
+    }
+  }
+
+  /** Updates the state of a branch that has already been added to the global
+   * history at 'position', where 'position' is 0-indexed and starts from the
+   * most recent history.  I.e., to update the most recently added branch
+   * outcome, 'position' would be 0.
+   * */
+  void updateHistory(bool isTaken, uint64_t position) {
+    if (position < size_) {
+      uint8_t vectIndex = position / 64;
+      uint8_t bitIndex = position % 64;
+      bool currentlyTaken = ((history_[vectIndex] & (1ull << bitIndex)) != 0);
+      if (currentlyTaken != isTaken) {
+        history_[vectIndex] ^= (1ull << bitIndex);
+      }
+    }
+  }
+
+  /** Removes the most recently added branch from the history */
+  void rollBack() {
+    for (uint8_t i = 0; i <= (size_ / 64); i++) {
+      history_[i] >>= 1;
+      if (i < (size_ / 64)) {
+        history_[i] |= (((history_[i + 1] & 1) > 0) ? (1ull << 63) : 0);
+      }
+    }
+  }
+
+ private:
+  /** The number of bits of branch history stored in this branch history */
+  uint64_t size_;
+
+  /** An array containing the bits of the branch history.  The bits are
+   * arranged such that the most recent branches are stored in uint64_t at
+   * index 0 of the vector, then the next most recent at index 1 and so forth.
+   * Within each uint64_t, the most recent branches are recorded in the
+   * least-significant bits. */
+  std::unique_ptr<uint64_t[]> history_;
+};
+
+}  // namespace simeng

src/include/simeng/branchpredictors/BranchPredictor.hh

@@ -12,7 +12,7 @@ namespace simeng {
 /** An abstract branch predictor interface. */
 class BranchPredictor {
  public:
-  virtual ~BranchPredictor(){};
+  virtual ~BranchPredictor() {};
 
   /** Generate a branch prediction for the supplied instruction address, a
    * branch type, and a known branch offset.  Returns a branch direction and

src/include/simeng/branchpredictors/GenericPredictor.hh

@@ -86,4 +86,4 @@ class GenericPredictor : public BranchPredictor {
   uint16_t rasSize_;
 };
 
-}  // namespace simeng
+}  // namespace simeng

src/include/simeng/branchpredictors/PerceptronPredictor.hh

@@ -102,4 +102,4 @@ class PerceptronPredictor : public BranchPredictor {
   uint64_t rasSize_;
 };
 
-}  // namespace simeng
+}  // namespace simeng