Prepare first release candidate #5

Paebbels · 2020-07-04T12:43:14Z

This will add:

AMBA
- AXI4
- AXI4-Lite
- AXI4-Stream
Common interfaces
- Tristate
- Differential signaling
- Differential lane
PoC
- CSE
Low-speed I/O buses
- I²C
- I²S
- SPI
- JTAG
- UART
Video
- VGA
- MIPI C-PHY
- MIPI D-PHY
- MIPI M-PHY
Ethernet
- MII
- GMII
- RGMII
- XGMII
- SGMII
Cages
- SFP
- QSFP

…d tristate interfaces.

This file has been successfully checked by Riviera-PRO 2020.04.

Paebbels · 2020-07-04T14:30:53Z

This will add some of the interfaces listed in #6.

…dded ReST prolog file.

IO/Common.vhdl

This file has been successfully checked by Riviera-PRO 2020.04.

LarsAsplund

Again some very high-level comments without diving into the actual standards

LarsAsplund · 2020-07-14T15:43:37Z

IO/Cages.vhdl

+	alias SFP_CageView is SFP_ICView'converse;
+
+	type SFP_Interface_Vector is
+		array(natural range <>)


In general I think we should use integer ranges. I find the natural ranges of some of the standard vector types limiting at times. Can't come up with a good example for negative indices here but I don't think we should add such a restriction unless we have very good reasons for that.

As natural is a subtype of integer, the range could be extended later if a usecase requires it. Such a change is backward compatible.

LarsAsplund · 2020-07-14T15:54:26Z

IO/Common.vhdl

+
+	-- Tristate (3-state) interface
+	type Tristate_Interface is record
+		I : std_logic;      -- Input


If there is a need to comment the meaning of an identifier the identifier should probably be renamed

The question for the whole repository should be if we:

follow original naming of standards, because many developers might be used to such naming.

minimally cleaning up names to unify naming across interfaces and packages in that repository

fully cleaning up all names

LarsAsplund · 2020-07-14T15:57:31Z

IO/I2S.vhdl

+use     IEEE.std_logic_1164.all;
+
+-- Signal name mappings
+-- SCK -> Serial Clock; alternatives: BCLK


Another example when I think we can use the full name rather than the abbreviation. Assuming we accept the interface to standar mismatch (I do)

LarsAsplund · 2020-07-14T15:59:28Z

IO/UART.vhdl

+-- RX -> Receive Data (RxD)
+package UART is
+	type UART_Interface is record
+		RX : std_logic;


This is an example where I think the abbreviation is very well established/understood.

LarsAsplund · 2020-07-14T16:01:16Z

PoC/CSE.vhdl

+-- =============================================================================
+-- Authors:         Patrick Lehmann
+--
+-- Generic Package: VHDL-2019 Command-Status-Error interface description


Is this according to some standard?

This is a commonly used interface in the PoC library - hence the path to the package. It's used in layered designs in combination with hierarchical state machines.

(cherry picked from commit 506bb3c25320137028aebc19f141362620878842)

Paebbels · 2023-05-19T15:01:02Z

@LarsAsplund, @JimLewis, @lievenlemiengre, @cmarqu, @umarcor, @nickg, @BAHayhoe, @pblecua, @martinjthompson, @brimdavis, @Nic30, @NJDFan, @tgingold, @M-KraftKugler, @MortenZdk, @tmeissner, @yyde, @marlonjames, @bradleyharden

There is now support for "interfaces" in Xilinx Vivado 2023.1 - so a first synthesis tool can use this stuff. I tested the code and except for some minor syntax updates, it was accepted by the tool.

AXI4-Lite

tgingold · 2023-05-22T17:01:56Z

At many places, you create an alias of the converse attribute of a mode view.

I don't think this is allowed by the LRM, as you can only alias a named entity.
(Even if this is used in an example of the LRM).

Probably the LRM needs to be fixed.

Paebbels · 2023-05-22T18:44:26Z

@tgingold

From LRM 6.6 Alias:

An object alias is an alias whose alias designator denotes an object (i.e., a constant, a variable, a signal, or a file). A nonobject alias is an alias whose alias designator denotes some named entity other than an object. An alias can be declared for all named entities except for labels, loop parameters, and generate parameters.

So, alias to views fall under nonobject alias.
Now the question is, what is a named alias?

From LRM 7.2 Attribute Specification, we know that named entities can be decorated with attributes. That' allowed for:

entity_class ::=
entity
| architecture
| configuration
| procedure
| function
| package
| type
| subtype
| constant
| signal
| variable
| component
| label
| literal
| units
| group
| file
| property
| sequence
| view

In LRM 16.2.5 Predefined attributes of named entities, we see attribute 'simple_name refers to LRM 7.2 for what is a list of named entities.

In Glossary we find:

named entity: An item associated with an identifier, character literal, or operator symbol as the result of an explicit or implicit declaration. (6.1) See also: name.

What would be missing to use an alias with a view returned from an attribute?

Paebbels · 2023-05-22T18:47:09Z

Oh, it's not listed in 6.1 Declarations → General.

tgingold · 2023-05-22T19:51:26Z

Yes. I think mode view declarations must be added in the 6.1 list, and probably there must be a special case for 'converse.

Paebbels · 2023-05-22T20:43:17Z

I created https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/293 to adjust the LRM.

nickg · 2023-05-22T21:06:43Z

So what should a conforming VHDL-2019 implementation do here: error on an alias of 'converse as required by the LRM or allow it as a special exception?

Paebbels · 2023-05-22T21:20:08Z

@nickg I think an error is not needed, as views where added in many places like LRM 7.2 to allow such an alias. Also by writing examples and adding a 'converse attribute the LCS writers (Jim, me, others) intended to allow aliases to such attributes. Without an alias this attribute is almost meaningless.

Also the discussion in http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/LCS2016_045c shows clearly the intentions by the the LCS authors to allow aliases.

So we should consider this an LRM bug / oversight and fix it in the next revision. That's why I created an issue in the LRM repository.

If your tool has a special mode / flag to allow non LRM (fully) compliant features, you could activate aliases in such a feature and keep your tool "pedantic" (that's how commercial tools call there inverse flag) until the LRM is fixed.

@nickg does this answer help you and your tool?

JimLewis · 2023-05-22T21:35:29Z

If your tool has a special mode / flag to allow non LRM (fully) compliant features, you could activate aliases in such a feature and keep your tool "pedantic" (that's how commercial tools call there inverse flag) until the LRM is fixed.

There is no benefit to requiring a "pedantic" flag for this. Based on the examples and referenced discussions, it is clear that the LRM committee intended that this feature be a named entity. Hence, I recommend that the LRM is interpreted as if views were included in the list of declarations in 6.1.

The problem with a pedantic off flag for this is that other things may also be allowed by the pedantic off flag that are not desired.

JimLewis · 2023-05-22T21:47:03Z

Isn't it a problem in the LRM that we have that bullet list in 6.1 and the bnf for entity_class. Aren't these redundant. It seems the LRM would benefit of the definition of entity_class were to replace the bullet list of 6.1 for the definition of named entity.

Redundant things are hard to maintain.

Paebbels · 2023-05-22T21:49:39Z

As I specified the change to entity_class in the LCS, I was not aware of a needed change to LRM 6.1.

nickg · 2023-05-29T20:43:46Z

The master branch of nickg/nvc has some preliminary support for interfaces. I'd welcome any testing/feedback.

nickg · 2023-05-29T20:44:32Z

IO/Common.vhdl

+
+package Common is
+	-- Differential signaling (DS or LVDS)
+	type Differatial_Interface is record


Suggested change

type Differatial_Interface is record

type Differential_Interface is record

Good catch, I'll search where I used that type elsewhere.

Paebbels and others added 10 commits July 4, 2020 13:13

Added common interfaces for differential signals, high-speed lanes an…

0dfcb89

…d tristate interfaces.

Added I²C interface descriptions.

db96c57

Added JTAG interface.

a7663b1

Added SPI interface.

35489e8

Fixed package name and signal name mappings.

4a17103

Added license text.

419863f

Added license text.

9fb05fc

Added license text.

582593b

Added DS for differential signaling to T_Lane. Added license text.

c7f12f6

Merged common interfaces

0767550

This file has been successfully checked by Riviera-PRO 2020.04.

Paebbels added Low-Speed I/O Low-speed I/O interface Common Interface Common I/O interface Serial Interface Serial communication interface External Mainly external interface between ICs on a PCB or similar. labels Jul 4, 2020

Paebbels self-assigned this Jul 4, 2020

Paebbels added 3 commits July 4, 2020 14:44

Merged i2c

83b6619

This file has been successfully checked by Riviera-PRO 2020.04.

Merged jtag

ed29bbb

This file has been successfully checked by Riviera-PRO 2020.04.

Merged SPI

c5e528a

This file has been successfully checked by Riviera-PRO 2020.04.

Paebbels marked this pull request as ready for review July 4, 2020 12:47

Paebbels requested review from eine, JimLewis, LarsAsplund, lievenlemiengre, pblecua and tgingold July 4, 2020 12:48

Paebbels added 3 commits July 4, 2020 16:39

Added Command-Status-Error interface.

699a2d0

Added initial documentation.

ca12d94

Fixed yml formatting for RTD. Extended conf.py. Added license file. A…

2083138

…dded ReST prolog file.

JimLewis reviewed Jul 4, 2020

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Paebbels and others added 8 commits July 5, 2020 18:35

Added physical interfaces for cages like SFP and QSFP.

6413ed5

Merged Cages

1f7d22d

This file has been successfully checked by Riviera-PRO 2020.04.

Updated after style reviews.

f8abd03

Added predefined constants for AXI4.

4bf6fb5

Added missing Cache field in AXI4-Lite.

c3d53ca

Added implementation for AXI4-Stream.

24b8cb5

Added AXI4 definitions (incomplete).

995b4b3

Added MIPI C-PHY interface.

f85b760

LarsAsplund reviewed Jul 14, 2020

View reviewed changes

Paebbels and others added 8 commits May 19, 2023 00:23

Renamed Sender to Transmitter in UART protocol.

cd82571

(cherry picked from commit 506bb3c25320137028aebc19f141362620878842)

Specified generic types in CSE package as enumeration types.

a9c279c

Merge branch 'AXI' into dev

9cab69e

Merge branch 'Ethernet' into dev

a92ecae

Added MIPI M-PHY interface.

9211893

Merge branch 'MIPI' into dev

9c3d619

Merge branch 'VGA' into dev

0c6ba95

Updated file headers.

24223c3

nickg reviewed May 29, 2023

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Prepare first release candidate #5

Prepare first release candidate #5

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	type Differatial_Interface is record
	type Differential_Interface is record

Prepare first release candidate #5

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Prepare first release candidate #5

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