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Prepare first release candidate #5

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Prepare first release candidate #5

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Commits on Jul 4, 2020

  1. Added common interfaces for differential signals, high-speed lanes an… 

    …d tristate interfaces.
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  2. Added I²C interface descriptions.

    @Paebbels
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  3. Added JTAG interface.

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  4. Added SPI interface.

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  5. Fixed package name and signal name mappings.

    @Paebbels
    Paebbels committed Jul 4, 2020
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  6. Added license text.

    @Paebbels
    Paebbels committed Jul 4, 2020
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  7. Added license text.

    @Paebbels
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  8. Added license text.

    @Paebbels
    Paebbels committed Jul 4, 2020
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  9. Added DS for differential signaling to T_Lane. Added license text.

    @Paebbels
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  10. Merged common interfaces 

    This file has been successfully checked by Riviera-PRO 2020.04.
    @Paebbels
    Paebbels authored Jul 4, 2020
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  11. Merged i2c 

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    @Paebbels
    Paebbels authored Jul 4, 2020
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  12. Merged jtag 

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    @Paebbels
    Paebbels authored Jul 4, 2020
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  13. Merged SPI 

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    @Paebbels
    Paebbels authored Jul 4, 2020
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  14. Added Command-Status-Error interface.

    @Paebbels
    Paebbels committed Jul 4, 2020
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  15. Added initial documentation.

    @Paebbels
    Paebbels committed Jul 4, 2020
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  16. Fixed yml formatting for RTD. Extended conf.py. Added license file. A… 

    …dded ReST prolog file.
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  17. Disabled recursive loading of main requirements file.

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    Paebbels committed Jul 4, 2020
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  18. This solves #10.

    @Paebbels
    Paebbels committed Jul 4, 2020
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  19. Fixed typo.

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    Paebbels committed Jul 4, 2020
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Commits on Jul 5, 2020

  1. Added common types for AXI4.

    @Paebbels
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  2. Added unconstraint interface description for AXI4-Lite.

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  3. Added generic package, so commonly used presized AXI interface can be… 

    … declared via package instances.
    @Paebbels
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  4. Added commonly used presized AXI4-Lite interfaces.

    @Paebbels
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  5. Added views.

    @Paebbels
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  6. Merged CSE 

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    @Paebbels
    Paebbels authored Jul 5, 2020
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  7. Added UART interface and views.

    @Paebbels
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  8. Merged UART 

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    @Paebbels
    Paebbels authored Jul 5, 2020
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  9. Added VGA interface.

    @Paebbels
    Paebbels committed Jul 5, 2020
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  10. Added I²S interface.

    @Paebbels
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  11. Merged I2S 

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    @Paebbels
    Paebbels authored Jul 5, 2020
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  12. Merge pull request #12 from VHDL/naming 

    Changed type and view naming
    @Paebbels
    Paebbels authored Jul 5, 2020
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  13. Merge pull request #11 from VHDL/documentation 

    Initial Documentation Skeleton
    @Paebbels
    Paebbels authored Jul 5, 2020
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  14. Added draft for Ethernet related interfaces (RMII, MII, RGMII, GMII, … 

    …XGMII, SGMII, QSGMII).
    @Paebbels
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  15. Added MIPI D-PHY interface.

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  16. Fixed data in MIPI D-PHY to use an 'array mode view indication'.

    @Paebbels
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  17. Added physical interfaces for cages like SFP and QSFP.

    @Paebbels
    Paebbels committed Jul 5, 2020
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  18. Merged Cages 

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    @Paebbels
    Paebbels authored Jul 5, 2020
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Commits on Jul 6, 2020

  1. Updated after style reviews.

    @Paebbels
    Paebbels committed Jul 6, 2020
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  2. Added predefined constants for AXI4.

    @Paebbels
    Paebbels committed Jul 6, 2020
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  3. Added missing Cache field in AXI4-Lite.

    @Paebbels
    Paebbels committed Jul 6, 2020
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  4. Added implementation for AXI4-Stream.

    @Paebbels
    Paebbels committed Jul 6, 2020
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  5. Added AXI4 definitions (incomplete).

    @Paebbels
    Paebbels committed Jul 6, 2020
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  6. Added MIPI C-PHY interface.

    @Paebbels
    Paebbels committed Jul 6, 2020
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Commits on May 18, 2023

  1. Renamed Sender to Transmitter in UART protocol. 

    (cherry picked from commit 506bb3c25320137028aebc19f141362620878842)
    @Paebbels
    Paebbels committed May 18, 2023
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  2. Specified generic types in CSE package as enumeration types.

    @Paebbels
    Paebbels committed May 18, 2023
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  3. Merge branch 'AXI' into dev

    @Paebbels
    Paebbels committed May 18, 2023
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  4. Merge branch 'Ethernet' into dev

    @Paebbels
    Paebbels committed May 18, 2023
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  5. Added MIPI M-PHY interface.

    @Paebbels
    Paebbels committed May 18, 2023
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  6. Merge branch 'MIPI' into dev

    @Paebbels
    Paebbels committed May 18, 2023
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  7. Merge branch 'VGA' into dev

    @Paebbels
    Paebbels committed May 18, 2023
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Commits on May 19, 2023

  1. Updated file headers.

    @Paebbels
    Paebbels committed May 19, 2023
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