Created artix and kintexu device files

byuccl · Jan 18, 2018 · 97c3ff7 · 97c3ff7
1 parent ae85e3d
commit 97c3ff7
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Showing 3 changed files with 57 additions and 50 deletions.
diff --git a/devices/artix7/xc7a100tcsg324_db.dat b/devices/artix7/xc7a100tcsg324_db.dat
diff --git a/devices/kintexu/xcku025ffva1156_db.dat b/devices/kintexu/xcku025ffva1156_db.dat
diff --git a/src/test/kotlin/edu/byu/ece/rapidSmith/device/ReverseWireConnectionsTest.kt b/src/test/kotlin/edu/byu/ece/rapidSmith/device/ReverseWireConnectionsTest.kt
@@ -7,77 +7,84 @@ import org.junit.Test
  * Tests that all forward connections have a reverse connection.
  */
 class ReverseWireConnectionsTest {
-	@Test fun testV6TileWires() {
-//		val device = Device.getInstance("xc6vlx75tff484");
-		val device = Device.getInstance("xc7a100tcsg324");
-		for (tile in device.tileMap.values) {
-			for (source in tile.wires) {
-				for (sinkConn in source.wireConnections) {
-					val sink = sinkConn.sinkWire
-
-					val rconns = sink.reverseWireConnections
-					val sinkSources = rconns.filter { it.sinkWire == source }
-
-					assert(sinkSources.size < 2) { "Multiple reverse connections found $sink -> $source" }
-					assert(sinkSources.isNotEmpty()) { "No reverse connections found $sink -> $source" }
-
-					val sinkSource = sinkSources[0]
-					assertEquals(sinkConn.isPip, sinkSource.isPip)
-				}
-			}
-
-			for (sink in tile.wires) {
-				for (sourceConn in sink.reverseWireConnections) {
-					val source = sourceConn.sinkWire
-
-					val conns = source.wireConnections
-					val sourceSinks = conns.filter { it.sinkWire == sink }
-
-					assert(sourceSinks.size < 2) { "Multiple reverse connections found $source -> $sink" }
-					assert(sourceSinks.isNotEmpty()) { "No reverse connections found $source -> $sink" }
-
-					val sourceSink = sourceSinks[0]
-					assertEquals(sourceConn.isPip, sourceSink.isPip)
-				}
-			}
-		}
-	}
-
-	@Test fun testV6SiteWires() {
-//		val device = Device.getInstance("xc6vlx75tff484");
-		val device = Device.getInstance("xc7a100tcsg324");
-		for (site in device.sites.values) {
-			for (type in site.possibleTypes) {
-				site.type = type
-				for (source in site.wires) {
+	val deviceNames = arrayOf("xc7a100tcsg324", "xcku025ffva1156");
+	@Test fun testReverseTileWires() {
+		for (dname in deviceNames) {
+			println("    ReverseWireConnectionsTest (tile wires) $dname");
+			val device = Device.getInstance(dname);
+
+			for (tile in device.tileMap.values) {
+				for (source in tile.wires) {
 					for (sinkConn in source.wireConnections) {
 						val sink = sinkConn.sinkWire
-
+	
 						val rconns = sink.reverseWireConnections
 						val sinkSources = rconns.filter { it.sinkWire == source }
-
+	
 						assert(sinkSources.size < 2) { "Multiple reverse connections found $sink -> $source" }
 						assert(sinkSources.isNotEmpty()) { "No reverse connections found $sink -> $source" }
-
+	
 						val sinkSource = sinkSources[0]
 						assertEquals(sinkConn.isPip, sinkSource.isPip)
 					}
 				}
-				for (sink in site.wires) {
+
+				for (sink in tile.wires) {
 					for (sourceConn in sink.reverseWireConnections) {
 						val source = sourceConn.sinkWire
-
+	
 						val conns = source.wireConnections
 						val sourceSinks = conns.filter { it.sinkWire == sink }
-
+	
 						assert(sourceSinks.size < 2) { "Multiple reverse connections found $source -> $sink" }
 						assert(sourceSinks.isNotEmpty()) { "No reverse connections found $source -> $sink" }
-
+	
 						val sourceSink = sourceSinks[0]
 						assertEquals(sourceConn.isPip, sourceSink.isPip)
 					}
 				}
 			}
 		}
 	}
+
+	@Test fun testReverseSiteWires() {
+		for (dname in deviceNames) {
+			println("    ReverseWireConnectionsTest (site wires) $dname");
+			val device = Device.getInstance(dname);
+
+			for (site in device.sites.values) {
+				for (type in site.possibleTypes) {
+					site.type = type
+					for (source in site.wires) {
+						for (sinkConn in source.wireConnections) {
+							val sink = sinkConn.sinkWire
+
+							val rconns = sink.reverseWireConnections
+							val sinkSources = rconns.filter { it.sinkWire == source }
+
+							assert(sinkSources.size < 2) { "Multiple reverse connections found $sink -> $source" }
+							assert(sinkSources.isNotEmpty()) { "No reverse connections found $sink -> $source" }
+
+							val sinkSource = sinkSources[0]
+						assertEquals(sinkConn.isPip, sinkSource.isPip)
+						}
+					}
+					for (sink in site.wires) {
+						for (sourceConn in sink.reverseWireConnections) {
+							val source = sourceConn.sinkWire
+
+							val conns = source.wireConnections
+							val sourceSinks = conns.filter { it.sinkWire == sink }
+
+							assert(sourceSinks.size < 2) { "Multiple reverse connections found $source -> $sink" }
+							assert(sourceSinks.isNotEmpty()) { "No reverse connections found $source -> $sink" }
+
+							val sourceSink = sourceSinks[0]
+							assertEquals(sourceConn.isPip, sourceSink.isPip)
+						}
+					}
+				}
+			}
+		}
+	}
 }