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minor updates based on feedback
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steph-morton committed Oct 25, 2023
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Expand Up @@ -40,7 +40,7 @@ The following figure shows the Caliptra Core.

## Boot Media Dependent (passive) vs Boot Media Integrated (active) profile

In the BMD profile, QSPI and I3C IO peripherals are disabled using integration-time defines passed to the hardware, which are also exposed to ROM. Peripheral IOs can be tied off appropriately for the BMD profile at SoC integration time. For more information on the passive vs. active profile differences, see the boot flows in[ Caliptra profiles](https://chipsalliance.github.io/Caliptra/doc/Caliptra.html#caliptra-profiles). Only the BMD profile is supported for the first generation release of Caliptra.
In the BMD profile, QSPI and I3C IO peripherals are disabled using integration-time defines passed to the hardware, which are also exposed to ROM. Peripheral IOs can be tied off appropriately for the BMD profile at SoC integration time. For more information on the BMD vs. BMI profile differences, see the boot flows in [Caliptra profiles](https://chipsalliance.github.io/Caliptra/doc/Caliptra.html#caliptra-profiles). Only the BMD profile is supported for the first generation release of Caliptra.

# SoC interface definition

Expand All @@ -65,7 +65,7 @@ The following table describes integration parameters.
| CPTRA_SET_FUSE_PAUSER_INTEG | 1 | Sets the valid PAUSER for fuse accesses at integration time. |
| CPTRA_FUSE_VALID_PAUSER | 32 | Overrides the programmable valid PAUSER for fuse accesses when CPTRA_SET_FUSE_PAUSER_INTEG is set to 1. |

*Table 3*
*Table 3: Integration Defines*

| **Defines** | **Description** |
| :--------- | :--------- |
Expand Down Expand Up @@ -203,7 +203,7 @@ De-assertion of cptra\_rst\_b indicates a warm reset cycle that resets all but t

### APB arbitration

Caliptra is a “slave” on the APB bus. If SoCs have multiple APBs or other proprietary-fabric protocols that require any special fabric arbitration, that arbitration is done at SoC level.
Caliptra is a client on the APB bus, incapable of initiating transfers. If SoCs have multiple APBs or other proprietary-fabric protocols that require any special fabric arbitration, that arbitration is done at SoC level.

### Undefined address accesses

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