Intercept latest RV core updates from VeeR repo

src/riscv_core/veer_el2/rtl/common_defines.sv

@@ -16,9 +16,9 @@
 
 
 // NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
-// This is an automatically generated file by cwhitehead on Wed Nov 13 10:25:09 PST 2024
+// This is an automatically generated file by cwhitehead on Wed Nov 20 18:12:03 PST 2024
 //
-// cmd:    veer -target=default_ahb -set=ret_stack_size=8 -set=btb_enable=1 -set=btb_fullya=0 -set=btb_size=512 -set=bht_size=512 -set=div_bit=4 -set=div_new=1 -set=dccm_enable=1 -set=dccm_num_banks=4 -set=dccm_region=0x5 -set=dccm_offset=0x00000 -set=dccm_size=128 -set=dma_buf_depth=5 -set=fast_interrupt_redirect=1 -set=icache_enable=0 -set=icache_waypack=1 -set=icache_ecc=1 -set=icache_size=16 -set=icache_2banks=1 -set=icache_num_ways=2 -set=icache_bypass_enable=1 -set=icache_num_bypass=2 -set=icache_num_tag_bypass=2 -set=icache_tag_bypass_enable=1 -set=iccm_enable=1 -set=iccm_num_banks=4 -set=iccm_region=0x4 -set=iccm_offset=0x0 -set=iccm_size=128 -set=lsu_stbuf_depth=4 -set=lsu_num_nbload=4 -set=load_to_use_plus1=0 -set=pic_2cycle=0 -set=pic_region=0x6 -set=pic_offset=0 -set=pic_size=32 -set=pic_total_int=31 -set=dma_buf_depth=5 -set=timer_legal_en=1 -set=bitmanip_zba=1 -set=bitmanip_zbb=1 -set=bitmanip_zbc=1 -set=bitmanip_zbe=0 -set=bitmanip_zbf=0 -set=bitmanip_zbp=0 -set=bitmanip_zbr=0 -set=bitmanip_zbs=1 -set=pmp_entries=64 -set=reset_vec=0x00000000 -fpga_optimize=0 -snapshot=20241106_cptra_en_pmp 
+// cmd:    veer -target=default_ahb -set=ret_stack_size=8 -set=btb_enable=1 -set=btb_fullya=0 -set=btb_size=512 -set=bht_size=512 -set=div_bit=4 -set=div_new=1 -set=dccm_enable=1 -set=dccm_num_banks=4 -set=dccm_region=0x5 -set=dccm_offset=0x00000 -set=dccm_size=128 -set=dma_buf_depth=5 -set=fast_interrupt_redirect=1 -set=icache_enable=0 -set=icache_waypack=1 -set=icache_ecc=1 -set=icache_size=16 -set=icache_2banks=1 -set=icache_num_ways=2 -set=icache_bypass_enable=1 -set=icache_num_bypass=2 -set=icache_num_tag_bypass=2 -set=icache_tag_bypass_enable=1 -set=iccm_enable=1 -set=iccm_num_banks=4 -set=iccm_region=0x4 -set=iccm_offset=0x0 -set=iccm_size=128 -set=lsu_stbuf_depth=4 -set=lsu_num_nbload=4 -set=load_to_use_plus1=0 -set=pic_2cycle=0 -set=pic_region=0x6 -set=pic_offset=0 -set=pic_size=32 -set=pic_total_int=31 -set=dma_buf_depth=5 -set=timer_legal_en=1 -set=bitmanip_zba=1 -set=bitmanip_zbb=1 -set=bitmanip_zbc=1 -set=bitmanip_zbe=0 -set=bitmanip_zbf=0 -set=bitmanip_zbp=0 -set=bitmanip_zbr=0 -set=bitmanip_zbs=1 -set=pmp_entries=64 -set=reset_vec=0x00000000 -fpga_optimize=0 -snapshot=20241120_latest_fixes 
 //
 `ifndef RV_COMMON_DEFINES
 `define RV_COMMON_DEFINES

src/riscv_core/veer_el2/rtl/dbg/el2_dbg.sv

@@ -133,7 +133,10 @@ import el2_pkg::*;
    input logic                         rst_l,        // This includes both top rst and debug rst
    input logic                         dbg_rst_l,
    input logic                         clk_override,
+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
    input logic                         scan_mode
+   /*verilator coverage_on*/
 );
 
 

src/riscv_core/veer_el2/rtl/dec/el2_dec.sv

@@ -320,7 +320,10 @@ module el2_dec
     output logic dec_tlu_icm_clk_override,    // override ICCM clock domain gating
 
     output logic dec_tlu_i0_commit_cmt,  // committed i0 instruction
+    // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+    /*verilator coverage_off*/
     input  logic scan_mode               // Flop scan mode control
+    /*verilator coverage_on*/
 
 );
 

src/riscv_core/veer_el2/rtl/dec/el2_dec_decode_ctl.sv

@@ -196,7 +196,10 @@ import el2_pkg::*;
 
    output logic       dec_div_active,                 // non-block divide is active
 
+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
    input  logic       scan_mode
+   /*verilator coverage_on*/
    );
 
 

src/riscv_core/veer_el2/rtl/dec/el2_dec_gpr_ctl.sv

@@ -39,7 +39,10 @@ import el2_pkg::*;
     output logic [31:0] rd0,         // read data
     output logic [31:0] rd1,
 
+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
     input  logic        scan_mode
+   /*verilator coverage_on*/
 );
 
    logic [31:1] [31:0] gpr_out;      // 31 x 32 bit GPRs

src/riscv_core/veer_el2/rtl/dec/el2_dec_pmp_ctl.sv

@@ -58,7 +58,10 @@ module el2_dec_pmp_ctl
    output el2_pmp_cfg_pkt_t pmp_pmpcfg  [pt.PMP_ENTRIES],
    output logic [31:0]      pmp_pmpaddr [pt.PMP_ENTRIES],
 
+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
    input  logic        scan_mode
+   /*verilator coverage_on*/
    );
 
    logic wr_pmpcfg_r;

src/riscv_core/veer_el2/rtl/dec/el2_dec_tlu_ctl.sv

@@ -33,7 +33,10 @@ import el2_pkg::*;
    input logic free_clk,
    input logic free_l2clk,
    input logic rst_l,
+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
    input logic scan_mode,
+   /*verilator coverage_on*/
 
    input logic [31:1] rst_vec, // reset vector, from core pins
    input logic        nmi_int, // nmi pin
@@ -3030,7 +3033,10 @@ import el2_pkg::*;
    output logic        dec_timer_t0_pulse, // timer0 int
    output logic        dec_timer_t1_pulse, // timer1 int
 
+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
    input  logic        scan_mode
+   /*verilator coverage_on*/
    );
    localparam MITCTL_ENABLE             = 0;
    localparam MITCTL_ENABLE_HALTED      = 1;

src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv

@@ -31,7 +31,10 @@ import el2_pkg::*;
    input logic         rst_l,
    input logic         dma_bus_clk_en, // slave bus clock enable
    input logic         clk_override,
+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
    input logic         scan_mode,
+   /*verilator coverage_on*/
 
    // Debug signals
    input logic [31:0]  dbg_cmd_addr,

src/riscv_core/veer_el2/rtl/el2_mem.sv

@@ -85,7 +85,10 @@ import el2_pkg::*;
 
    el2_mem_if.veer_sram_src mem_export,
 
+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
    input  logic         scan_mode
+   /*verilator coverage_on*/
 
 );
 

src/riscv_core/veer_el2/rtl/el2_pic_ctrl.sv

@@ -47,7 +47,10 @@ import el2_pkg::*;
                      output logic [3:0]             pl,                   // Priority level of the requested interrupt
                      output logic [31:0]            picm_rd_data,         // Read data of the register
                      output logic                   mhwakeup,             // Wake-up interrupt request
+                     // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+                     /*verilator coverage_off*/
                      input  logic                   scan_mode             // scan mode
+                     /*verilator coverage_on*/
 
 );
 

src/riscv_core/veer_el2/rtl/el2_veer.sv

@@ -458,7 +458,10 @@ import el2_pkg::*;
    input logic [pt.PIC_TOTAL_INT:1]           extintsrc_req,
    input logic                   timer_int,
    input logic                   soft_int,
+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
    input logic                   scan_mode
+   /*verilator coverage_on*/
 );
 
 

src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv

@@ -428,7 +428,7 @@ import el2_pkg::*;
    input logic                             i_cpu_run_req, // Async restart req to CPU
    output logic                            o_cpu_run_ack, // Core response to run req
 
-   /* exclude signals that are tied to constant value or left unconnected in tb_top.sv */
+   // Excluding scan_mode and mbist_mode from coverage as their usage is determined by the integrator of the VeeR core.
    /* verilator coverage_off */
    input logic                             scan_mode,     // To enable scan mode
    input logic                             mbist_mode,    // to enable mbist

src/riscv_core/veer_el2/rtl/exu/el2_exu.sv

@@ -22,7 +22,10 @@ import el2_pkg::*;
   (
    input logic          clk,                                           // Top level clock
    input logic          rst_l,                                         // Reset
+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
    input logic          scan_mode,                                     // Scan control
+   /*verilator coverage_on*/
 
    input logic  [1:0]   dec_data_en,                                   // Clock enable {x,r}, one cycle pulse
    input logic  [1:0]   dec_ctl_en,                                    // Clock enable {x,r}, two cycle pulse

src/riscv_core/veer_el2/rtl/exu/el2_exu_alu_ctl.sv

@@ -22,7 +22,10 @@ import el2_pkg::*;
   (
    input  logic                  clk,                // Top level clock
    input  logic                  rst_l,              // Reset
+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
    input  logic                  scan_mode,          // Scan control
+   /*verilator coverage_on*/
 
    input  logic                  flush_upper_x,      // Branch flush from previous cycle
    input  logic                  flush_lower_r,      // Master flush of entire pipeline

src/riscv_core/veer_el2/rtl/exu/el2_exu_div_ctl.sv

@@ -22,7 +22,10 @@ import el2_pkg::*;
   (
    input logic           clk,                       // Top level clock
    input logic           rst_l,                     // Reset
+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
    input logic           scan_mode,                 // Scan mode
+   /*verilator coverage_on*/
 
    input el2_div_pkt_t  dp,                        // valid, sign, rem
    input logic  [31:0]   dividend,                  // Numerator
@@ -140,7 +143,10 @@ module el2_exu_div_existing_1bit_cheapshortq
   (
    input  logic            clk,                       // Top level clock
    input  logic            rst_l,                     // Reset
+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
    input  logic            scan_mode,                 // Scan mode
+   /*verilator coverage_on*/
 
    input  logic            cancel,                    // Flush pipeline
    input  logic            valid_in,
@@ -448,7 +454,10 @@ module el2_exu_div_new_1bit_fullshortq
   (
    input  logic            clk,                       // Top level clock
    input  logic            rst_l,                     // Reset
+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
    input  logic            scan_mode,                 // Scan mode
+   /*verilator coverage_on*/
 
    input  logic            cancel,                    // Flush pipeline
    input  logic            valid_in,
@@ -706,7 +715,10 @@ module el2_exu_div_new_2bit_fullshortq
   (
    input  logic            clk,                       // Top level clock
    input  logic            rst_l,                     // Reset
+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
    input  logic            scan_mode,                 // Scan mode
+   /*verilator coverage_on*/
 
    input  logic            cancel,                    // Flush pipeline
    input  logic            valid_in,
@@ -980,7 +992,10 @@ module el2_exu_div_new_3bit_fullshortq
   (
    input  logic            clk,                       // Top level clock
    input  logic            rst_l,                     // Reset
+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
    input  logic            scan_mode,                 // Scan mode
+   /*verilator coverage_on*/
 
    input  logic            cancel,                    // Flush pipeline
    input  logic            valid_in,
@@ -1312,7 +1327,10 @@ module el2_exu_div_new_4bit_fullshortq
   (
    input  logic            clk,                       // Top level clock
    input  logic            rst_l,                     // Reset
+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
    input  logic            scan_mode,                 // Scan mode
+   /*verilator coverage_on*/
 
    input  logic            cancel,                    // Flush pipeline
    input  logic            valid_in,

src/riscv_core/veer_el2/rtl/exu/el2_exu_mul_ctl.sv

@@ -22,7 +22,10 @@ import el2_pkg::*;
   (
    input logic          clk,              // Top level clock
    input logic          rst_l,            // Reset
+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
    input logic          scan_mode,        // Scan mode
+   /*verilator coverage_on*/
 
    input el2_mul_pkt_t mul_p,            // {Valid, RS1 signed operand, RS2 signed operand, Select low 32-bits of result}
 

src/riscv_core/veer_el2/rtl/ifu/el2_ifu.sv

@@ -214,7 +214,10 @@ import el2_pkg::*;
    output logic                                iccm_buf_correct_ecc,
    output logic                                iccm_correction_state,
 
+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
    input logic scan_mode
+   /*verilator coverage_on*/
    );
 
    localparam TAGWIDTH = 2 ;

src/riscv_core/veer_el2/rtl/ifu/el2_ifu_aln_ctl.sv

@@ -25,7 +25,10 @@ import el2_pkg::*;
  )
   (
 
+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
    input logic                                    scan_mode,                // Flop scan mode control
+   /*verilator coverage_on*/
    input logic                                    rst_l,                    // reset, active low
    input logic                                    clk,                      // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
    input logic                                    active_clk,               // Clock only while core active.  Through two clock headers. For flops without second clock header built in.

src/riscv_core/veer_el2/rtl/ifu/el2_ifu_bp_ctl.sv

@@ -75,7 +75,10 @@ import el2_pkg::*;
 
    output logic [1:0] [$clog2(pt.BTB_SIZE)-1:0]    ifu_bp_fa_index_f, // predicted branch index (fully associative option)
 
+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
    input  logic       scan_mode
+   /*verilator coverage_on*/
    );
 
 

src/riscv_core/veer_el2/rtl/ifu/el2_ifu_ic_mem.sv

@@ -54,7 +54,10 @@ import el2_pkg::*;
 
       output logic [pt.ICACHE_NUM_WAYS-1:0]         ic_rd_hit,          // ic_rd_hit[3:0]
       output logic                                  ic_tag_perr,        // Tag Parity error
+      // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+      /*verilator coverage_off*/
       input  logic                                  scan_mode           // Flop scan mode control
+      /*verilator coverage_on*/
       ) ;
 
 
@@ -113,7 +116,10 @@ import el2_pkg::*;
 
       input logic [pt.ICACHE_NUM_WAYS-1:0]ic_rd_hit,
       input el2_ic_data_ext_in_pkt_t  [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,   // this is being driven by the top level for soc testing/etc
+      // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+      /*verilator coverage_off*/
       input  logic                         scan_mode
+      /*verilator coverage_on*/
 
       ) ;
 
@@ -824,7 +830,10 @@ import el2_pkg::*;
 
       output logic [pt.ICACHE_NUM_WAYS-1:0]                        ic_rd_hit,
       output logic                                                 ic_tag_perr,
+      // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+      /*verilator coverage_off*/
       input  logic                                                 scan_mode
+      /*verilator coverage_on*/
    ) ;
 
    logic [pt.ICACHE_NUM_WAYS-1:0] [25:0]                           ic_tag_data_raw;

src/riscv_core/veer_el2/rtl/ifu/el2_ifu_iccm_mem.sv

@@ -42,7 +42,10 @@ import el2_pkg::*;
 
    output logic [63:0]                                iccm_rd_data,                        // ICCM read data
    output logic [77:0]                                iccm_rd_data_ecc,                    // ICCM read ecc
+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
    input  logic                                       scan_mode                            // Scan mode control
+   /*verilator coverage_on*/
 
 );
 

src/riscv_core/veer_el2/rtl/ifu/el2_ifu_ifc_ctl.sv

@@ -30,7 +30,10 @@ import el2_pkg::*;
    input logic free_l2clk,                  // Clock always.                  Through one clock header.  For flops with    second header built in.
 
    input logic rst_l, // reset enable, from core pin
+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
    input logic scan_mode, // scan
+   /*verilator coverage_on*/
 
    input logic ic_hit_f,      // Icache hit
    input logic ifu_ic_mb_empty, // Miss buffer empty

src/riscv_core/veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv

@@ -194,7 +194,10 @@ import el2_pkg::*;
    input  logic                      ifu_pmp_error,
 
 
+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
    input  logic         scan_mode
+   /*verilator coverage_on*/
    );
 
 //  Create different defines for ICACHE and ICCM enable combinations

src/riscv_core/veer_el2/rtl/include/el2_dec_csr_equ_m.svh

@@ -50,6 +50,8 @@ logic csr_mitb0;
 logic csr_mitb1;
 logic csr_mitcnt0;
 logic csr_mitcnt1;
+/* exclude signals that are tied to constant value in this file */
+/*verilator coverage_off*/
 logic csr_perfva;
 logic csr_perfvb;
 logic csr_perfvc;
@@ -59,6 +61,7 @@ logic csr_perfvf;
 logic csr_perfvg;
 logic csr_perfvh;
 logic csr_perfvi;
+/*verilator coverage_on*/
 logic csr_mpmc;
 logic csr_mcpc;
 logic csr_meicpct;

src/riscv_core/veer_el2/rtl/lib/axi4_to_ahb.sv

@@ -30,7 +30,10 @@ import el2_pkg::*;
    input                   clk,
    input                   free_clk,
    input                   rst_l,
+   // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
+   /*verilator coverage_off*/
    input                   scan_mode,
+   /*verilator coverage_on*/
    input                   bus_clk_en,
    input                   clk_override,
    input                   dec_tlu_force_halt,