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Merge pull request #273 from chipsalliance/dev-msft-20231102
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Dev msft 20231102
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calebofearth authored Nov 3, 2023
2 parents 1448b38 + 92c6aea commit 92876e1
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Showing 10 changed files with 113 additions and 74 deletions.
12 changes: 8 additions & 4 deletions src/doe/rtl/doe_reg.rdl
Original file line number Diff line number Diff line change
Expand Up @@ -204,8 +204,10 @@ addrmap doe_reg {
reg error_intr_trig_t {
name = "Interrupt Trigger Register type definition";
desc = "Single bit for each interrupt event allows SW to manually
trigger occurrence of that event. Upon SW write, the bit
will pulse for 1 cycle then clear to 0.";
trigger occurrence of that event. Upon SW write, the trigger bit
will pulse for 1 cycle then clear to 0. The pulse on the
trigger register bit results in the corresponding interrupt
status bit being set to 1.";

default hw = na;
default sw = rw;
Expand All @@ -223,8 +225,10 @@ addrmap doe_reg {
reg notif_intr_trig_t {
name = "Interrupt Trigger Register type definition";
desc = "Single bit for each interrupt event allows SW to manually
trigger occurrence of that event. Upon SW write, the bit
will pulse for 1 cycle then clear to 0.";
trigger occurrence of that event. Upon SW write, the trigger bit
will pulse for 1 cycle then clear to 0. The pulse on the
trigger register bit results in the corresponding interrupt
status bit being set to 1.";

default hw = na;
default sw = rw;
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12 changes: 8 additions & 4 deletions src/ecc/rtl/ecc_reg.rdl
Original file line number Diff line number Diff line change
Expand Up @@ -455,8 +455,10 @@ addrmap ecc_reg {
reg error_intr_trig_t {
name = "Interrupt Trigger Register type definition";
desc = "Single bit for each interrupt event allows SW to manually
trigger occurrence of that event. Upon SW write, the bit
will pulse for 1 cycle then clear to 0.";
trigger occurrence of that event. Upon SW write, the trigger bit
will pulse for 1 cycle then clear to 0. The pulse on the
trigger register bit results in the corresponding interrupt
status bit being set to 1.";

default hw = na;
default sw = rw;
Expand All @@ -471,8 +473,10 @@ addrmap ecc_reg {
reg notif_intr_trig_t {
name = "Interrupt Trigger Register type definition";
desc = "Single bit for each interrupt event allows SW to manually
trigger occurrence of that event. Upon SW write, the bit
will pulse for 1 cycle then clear to 0.";
trigger occurrence of that event. Upon SW write, the trigger bit
will pulse for 1 cycle then clear to 0. The pulse on the
trigger register bit results in the corresponding interrupt
status bit being set to 1.";

default hw = na;
default sw = rw;
Expand Down
14 changes: 9 additions & 5 deletions src/hmac/rtl/hmac_reg.rdl
Original file line number Diff line number Diff line change
Expand Up @@ -281,8 +281,10 @@ addrmap hmac_reg {
reg error_intr_trig_t {
name = "Interrupt Trigger Register type definition";
desc = "Single bit for each interrupt event allows SW to manually
trigger occurrence of that event. Upon SW write, the bit
will pulse for 1 cycle then clear to 0.";
trigger occurrence of that event. Upon SW write, the trigger bit
will pulse for 1 cycle then clear to 0. The pulse on the
trigger register bit results in the corresponding interrupt
status bit being set to 1.";

default hw = na;
default sw = rw;
Expand All @@ -300,8 +302,10 @@ addrmap hmac_reg {
reg notif_intr_trig_t {
name = "Interrupt Trigger Register type definition";
desc = "Single bit for each interrupt event allows SW to manually
trigger occurrence of that event. Upon SW write, the bit
will pulse for 1 cycle then clear to 0.";
trigger occurrence of that event. Upon SW write, the trigger bit
will pulse for 1 cycle then clear to 0. The pulse on the
trigger register bit results in the corresponding interrupt
status bit being set to 1.";

default hw = na;
default sw = rw;
Expand Down Expand Up @@ -469,4 +473,4 @@ addrmap hmac_reg {
* ----------------------- */
intr_block_t intr_block_rf @0x800;

};
};
12 changes: 8 additions & 4 deletions src/libs/rtl/interrupt_regs.rdl
Original file line number Diff line number Diff line change
Expand Up @@ -141,8 +141,10 @@ addrmap interrupt_regs {
reg error_intr_trig_t {
name = "Interrupt Trigger Register type definition";
desc = "Single bit for each interrupt event allows SW to manually
trigger occurrence of that event. Upon SW write, the bit
will pulse for 1 cycle then clear to 0.";
trigger occurrence of that event. Upon SW write, the trigger bit
will pulse for 1 cycle then clear to 0. The pulse on the
trigger register bit results in the corresponding interrupt
status bit being set to 1.";

default hw = na;
default sw = rw;
Expand All @@ -160,8 +162,10 @@ addrmap interrupt_regs {
reg notif_intr_trig_t {
name = "Interrupt Trigger Register type definition";
desc = "Single bit for each interrupt event allows SW to manually
trigger occurrence of that event. Upon SW write, the bit
will pulse for 1 cycle then clear to 0.";
trigger occurrence of that event. Upon SW write, the trigger bit
will pulse for 1 cycle then clear to 0. The pulse on the
trigger register bit results in the corresponding interrupt
status bit being set to 1.";

default hw = na;
default sw = rw;
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -121,7 +121,7 @@ class ahb_lite_slave_0_config_policy;
// // If true, drives previous address when bus is IDLE
// cfg.m_bfm.config_address_on_idle = 1'b0;
// // Maximum number of successive wait states
cfg.m_bfm.config_max_wait_states_count = 32;
cfg.m_bfm.config_max_wait_states_count = 33;
// // Data endianness
// cfg.m_bfm.config_endianness = AHB_LITTLE_ENDIAN;
// // Sets the domain
Expand Down
12 changes: 8 additions & 4 deletions src/sha256/rtl/sha256_reg.rdl
Original file line number Diff line number Diff line change
Expand Up @@ -238,8 +238,10 @@ addrmap sha256_reg {
reg error_intr_trig_t {
name = "Interrupt Trigger Register type definition";
desc = "Single bit for each interrupt event allows SW to manually
trigger occurrence of that event. Upon SW write, the bit
will pulse for 1 cycle then clear to 0.";
trigger occurrence of that event. Upon SW write, the trigger bit
will pulse for 1 cycle then clear to 0. The pulse on the
trigger register bit results in the corresponding interrupt
status bit being set to 1.";

default hw = na;
default sw = rw;
Expand All @@ -257,8 +259,10 @@ addrmap sha256_reg {
reg notif_intr_trig_t {
name = "Interrupt Trigger Register type definition";
desc = "Single bit for each interrupt event allows SW to manually
trigger occurrence of that event. Upon SW write, the bit
will pulse for 1 cycle then clear to 0.";
trigger occurrence of that event. Upon SW write, the trigger bit
will pulse for 1 cycle then clear to 0. The pulse on the
trigger register bit results in the corresponding interrupt
status bit being set to 1.";

default hw = na;
default sw = rw;
Expand Down
14 changes: 9 additions & 5 deletions src/sha512/rtl/sha512_reg.rdl
Original file line number Diff line number Diff line change
Expand Up @@ -280,8 +280,10 @@ addrmap sha512_reg {
reg error_intr_trig_t {
name = "Interrupt Trigger Register type definition";
desc = "Single bit for each interrupt event allows SW to manually
trigger occurrence of that event. Upon SW write, the bit
will pulse for 1 cycle then clear to 0.";
trigger occurrence of that event. Upon SW write, the trigger bit
will pulse for 1 cycle then clear to 0. The pulse on the
trigger register bit results in the corresponding interrupt
status bit being set to 1.";

default hw = na;
default sw = rw;
Expand All @@ -299,8 +301,10 @@ addrmap sha512_reg {
reg notif_intr_trig_t {
name = "Interrupt Trigger Register type definition";
desc = "Single bit for each interrupt event allows SW to manually
trigger occurrence of that event. Upon SW write, the bit
will pulse for 1 cycle then clear to 0.";
trigger occurrence of that event. Upon SW write, the trigger bit
will pulse for 1 cycle then clear to 0. The pulse on the
trigger register bit results in the corresponding interrupt
status bit being set to 1.";

default hw = na;
default sw = rw;
Expand Down Expand Up @@ -467,4 +471,4 @@ addrmap sha512_reg {
* Register File instance
* ----------------------- */
intr_block_t intr_block_rf @0x800;
};
};
12 changes: 8 additions & 4 deletions src/soc_ifc/rtl/sha512_acc_csr.rdl
Original file line number Diff line number Diff line change
Expand Up @@ -125,8 +125,10 @@ addrmap sha512_acc_csr {
reg error_intr_trig_t {
name = "Interrupt Trigger Register type definition";
desc = "Single bit for each interrupt event allows SW to manually
trigger occurrence of that event. Upon SW write, the bit
will pulse for 1 cycle then clear to 0.";
trigger occurrence of that event. Upon SW write, the trigger bit
will pulse for 1 cycle then clear to 0. The pulse on the
trigger register bit results in the corresponding interrupt
status bit being set to 1.";

default hw = na;
default sw = rw;
Expand All @@ -145,8 +147,10 @@ addrmap sha512_acc_csr {
reg notif_intr_trig_t {
name = "Interrupt Trigger Register type definition";
desc = "Single bit for each interrupt event allows SW to manually
trigger occurrence of that event. Upon SW write, the bit
will pulse for 1 cycle then clear to 0.";
trigger occurrence of that event. Upon SW write, the trigger bit
will pulse for 1 cycle then clear to 0. The pulse on the
trigger register bit results in the corresponding interrupt
status bit being set to 1.";

default hw = na;
default sw = rw;
Expand Down
12 changes: 8 additions & 4 deletions src/soc_ifc/rtl/soc_ifc_internal_reg.rdl
Original file line number Diff line number Diff line change
Expand Up @@ -350,8 +350,10 @@ regfile intr_block_t {
reg error_intr_trig_t {
name = "Interrupt Trigger Register type definition";
desc = "Single bit for each interrupt event allows SW to manually
trigger occurrence of that event. Upon SW write, the bit
will pulse for 1 cycle then clear to 0.";
trigger occurrence of that event. Upon SW write, the trigger bit
will pulse for 1 cycle then clear to 0. The pulse on the
trigger register bit results in the corresponding interrupt
status bit being set to 1.";

default hw = na;
default sw = rw;
Expand All @@ -373,8 +375,10 @@ regfile intr_block_t {
reg notif_intr_trig_t {
name = "Interrupt Trigger Register type definition";
desc = "Single bit for each interrupt event allows SW to manually
trigger occurrence of that event. Upon SW write, the bit
will pulse for 1 cycle then clear to 0.";
trigger occurrence of that event. Upon SW write, the trigger bit
will pulse for 1 cycle then clear to 0. The pulse on the
trigger register bit results in the corresponding interrupt
status bit being set to 1.";

default hw = na;
default sw = rw;
Expand Down
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