Skip to content

Commit

Permalink
Revise crypto IP RDL descriptions (#480)
Browse files Browse the repository at this point in the history 
* revised rdl comments

* resolved the comments

* fixed typo

---------

Co-authored-by: Mojtaba Bisheh Niasar <[email protected]>
  • Loading branch information
@mojtaba-bisheh
mojtaba-bisheh and Mojtaba Bisheh Niasar authored Mar 28, 2024
1 parent 5e5e37f commit e365602
Show file tree
Hide file tree
Showing 4 changed files with 173 additions and 209 deletions.
151 changes: 67 additions & 84 deletions src/ecc/rtl/ecc_reg.rdl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -37,9 +37,8 @@ addrmap ecc_reg {
/* ---- ECC Component Name ---- */
reg {
name = "ECC component name register type definition";
desc = "Two 32-bit read-only registers repereseting of the name
of ECC component. These registers are located at
ECC_base_address + 0x0000_0000 and 0x0000_0004 addresses.";
desc = "Two 32-bit read-only registers representing of the name
of ECC component.";

default sw = r;
default hw = w;
Expand All @@ -52,9 +51,8 @@ addrmap ecc_reg {
/* ---- ECC Component Version ---- */
reg {
name = "ECC component version register type definition";
desc = "Two 32-bit read-only registers repereseting of the version
of ECC component. These registers are located at
ECC_base_address + 0x0000_0008 and 0x0000_000C addresses.";
desc = "Two 32-bit read-only registers representing of the version
of ECC component.";

default sw = r;
default hw = w;
Expand All @@ -66,54 +64,49 @@ addrmap ecc_reg {

/* ---- ECC Component Control ---- */
reg {
name = "ECC component control register type definition";
desc = "One 4-bit register to set the type of ECC operations.
[br] bit #[1:0]: This can be:
[br] 00 for NONE
[br] 01 for KEYGEN
[br] 10 for SIGNING
[br] 11 for VERIFYING
[br] bit #2: Zeroize all internal registers after ECC process, to avoid SCA leakage.
[br] bit #3: Run ECC Signing flow to sign PCRs.
[br] This register is located at ECC_base_address + 0x0000_0010.";
name = "ECC CTRL";
desc = "ECC component control register type definition";

default sw = w;
default hw = r;
default resetsignal = reset_b;
field {desc = "Control command field"; swwe = ecc_ready; hwclr;} CTRL[2] = 2'b0;
field {desc = "Zeroize all internal registers"; singlepulse;} ZEROIZE = 1'b0;
field {desc = "Run PCR Signing flow"; swwe = ecc_ready; hwclr;} PCR_SIGN = 1'b0;
field {desc = "Control command field: This can be:
[br] 00 for NONE
[br] 01 for KEYGEN
[br] 10 for SIGNING
[br] 11 for VERIFYING
[br] After each software write, hardware will erase the register"; swwe = ecc_ready; hwclr;} CTRL[2] = 2'b0;
field {desc = "Zeroize all internal registers: Zeroize all internal registers after ECC process, to avoid SCA leakage.
[br] Software write generates only a single-cycle pulse on the
hardware interface and then will be erased"; singlepulse;} ZEROIZE = 1'b0;
field {desc = "Run PCR Signing flow: Run ECC Signing flow to sign PCRs."; swwe = ecc_ready; hwclr;} PCR_SIGN = 1'b0;

} ECC_CTRL @0x00000010;



/* ---- ECC Component Status ---- */
reg {
name = "ECC component status register type definition";
desc = "One 2-bit register including the following flags:
bit #0: READY : ​Indicates if the core is ready to take
a control command and process the block.
bit #1: VALID : ​Indicates if the process is done and the
hash value stored in DIGEST registers is valid.
This register is located at ECC_base_address + 0x0000_0018.";
name = "ECC STATUS";
desc = "ECC component status register type definition";

default sw = r;
default hw = w;
default resetsignal = reset_b;
field {desc = "Status ready bit";} READY = 1'b0;
field {desc = "Status valid bit";} VALID = 1'b0;
field {desc = "Status ready bit: ​Indicates if the core is ready to take
a control command and process the block.";} READY = 1'b0;
field {desc = "Status valid bit: ​Indicates if the process is done and the
hash value stored in DIGEST registers is valid.";} VALID = 1'b0;

} ECC_STATUS @0x00000018;


/* ---- ECC Component Input SEED ---- */
reg {
name = "ECC component seed register type definition";
desc = "12 32-bit registers storing the 384-bit seed for keygen.
The seed can be any 384-bit value in [0 : 2^384-1].
These registers are located at ECC_base_address +
0x0000_0080 to 0x0000_00AC in big-endian representation.";
name = "ECC SEED";
desc = "ECC component seed register type definition
12 32-bit registers storing the 384-bit seed for keygen in big-endian representation.
The seed can be any 384-bit value in [0 : 2^384-1].";

default sw = w;
default hw = rw;
Expand All @@ -126,11 +119,10 @@ addrmap ecc_reg {

/* ---- ECC Component Input NONCE ---- */
reg {
name = "ECC component nonce register type definition";
desc = "12 32-bit registers storing the 384-bit nonce for keygen.
The nonce can be any 384-bit value in [0 : 2^384-1].
These registers are located at ECC_base_address +
0x0000_0500 to 0x0000_052C in big-endian representation.";
name = "ECC NONCE";
desc = "ECC component nonce register type definition
12 32-bit registers storing the 384-bit nonce for keygen in big-endian representation.
The nonce can be any 384-bit value in [0 : 2^384-1].";

default sw = w;
default hw = r;
Expand All @@ -143,12 +135,11 @@ addrmap ecc_reg {

/* ---- ECC Component Input Message ---- */
reg {
name = "ECC component hashed message register type definition";
desc = "12 32-bit registers storing the hash of the message respect
to SHA384 algorithm.
The hashed message can be any 384-bit value in [0 : 2^384-1].
These registers are located at ECC_base_address +
0x0000_0100 to 0x0000_012C in big-endian representation.";
name = "ECC_MSG";
desc = "ECC component hashed message register type definition
12 32-bit registers storing the hash of the message respect
to SHA384 algorithm in big-endian representation.
The hashed message can be any 384-bit value in [0 : 2^384-1].";

default sw = w;
default hw = rw;
Expand All @@ -162,13 +153,12 @@ addrmap ecc_reg {

/* ---- ECC Component Private Key OUT---- */
reg {
name = "ECC component private key output register type definition";
desc = "12 32-bit registers storing the private key for keygen.
name = "ECC PRIVKEY OUT";
desc = "ECC component private key output register type definition
12 32-bit registers storing the private key for keygen in big-endian representation.
These registers is read by ECC user after keygen operation.
The private key is in [1 : q-1] while q is the group
order of the Secp384r1 curve.
These registers are located at ECC_base_address +
0x0000_0180 to 0x0000_01AC in big-endian representation.";
order of the Secp384r1 curve.";

default sw = r;
default hw = w;
Expand All @@ -180,13 +170,12 @@ addrmap ecc_reg {

/* ---- ECC Component Private Key IN---- */
reg {
name = "ECC component private key input register type definition";
desc = "12 32-bit registers storing the private key for signing.
name = "ECC PRIVKEY IN";
desc = "ECC component private key input register type definition
12 32-bit registers storing the private key for signing in big-endian representation.
These registers is set before signing operation.
The private key should be in [1 : q-1] while q is the group
order of the Secp384r1 curve.
These registers are located at ECC_base_address +
0x0000_0580 to 0x0000_05AC in big-endian representation.";
order of the Secp384r1 curve.";

default sw = w;
default hw = rw;
Expand All @@ -199,14 +188,13 @@ addrmap ecc_reg {

/* ---- ECC Component Public Key x ---- */
reg {
name = "ECC component public key (x) register type definition";
desc = "12 32-bit registers storing the x coordinate of public key.
name = "ECC PUBKEY X";
desc = "ECC component public key (x) register type definition
12 32-bit registers storing the x coordinate of public key in big-endian representation.
These registers is read by ECC user after keygen operation,
or be set before verifying operation.
The public key x should be in [1 : p-1] while p is the prime
number of the Secp384r1 curve.
These registers are located at ECC_base_address +
0x0000_0200 to 0x0000_022C in big-endian representation.";
number of the Secp384r1 curve.";

default sw = rw;
default hw = rw;
Expand All @@ -219,14 +207,13 @@ addrmap ecc_reg {

/* ---- ECC Component Public Key y ---- */
reg {
name = "ECC component public key (y) register type definition";
desc = "12 32-bit registers storing the y coordinate of public key.
name = "ECC PUBKEY Y";
desc = "ECC component public key (y) register type definition
12 32-bit registers storing the y coordinate of public key in big-endian representation.
These registers is read by ECC user after keygen operation,
or be set before verifying operation.
The public key y should be in [1 : p-1] while p is the prime
number of the Secp384r1 curve.
These registers are located at ECC_base_address +
0x0000_0280 to 0x0000_02AC in big-endian representation.";
number of the Secp384r1 curve.";

default sw = rw;
default hw = rw;
Expand All @@ -240,17 +227,16 @@ addrmap ecc_reg {

/* ---- ECC Component Signature R ---- */
reg {
name = "ECC component signature R register type definition";
desc = "12 32-bit registers storing the signature R of the message.
name = "ECC SIGN R";
desc = "ECC component signature R register type definition
12 32-bit registers storing the signature R of the message in big-endian representation.
These registers is read by ECC user after signing operation,
or be set before verifying operation.
The signature R should be in [1 : q-1] while q is the group
order of the Secp384r1 curve.
Based on RFC6979, If R turns out to be zero, a new nonce (by changing
the private key or the message) should be selected and R computed
again (this is an utterly improbable occurrence).
These registers are located at ECC_base_address +
0x0000_0300 to 0x0000_032C in big-endian representation.";
again (this is an utterly improbable occurrence).";

default sw = rw;
default hw = rw;
Expand All @@ -264,14 +250,13 @@ addrmap ecc_reg {

/* ---- ECC Component Signature S ---- */
reg {
name = "ECC component signature S register type definition";
desc = "12 32-bit registers storing the signature S of the message.
name = "ECC SIGN S";
desc = "ECC component signature S register type definition
12 32-bit registers storing the signature S of the message in big-endian representation.
These registers is read by ECC user after signing operation,
or be set before verifying operation.
The signature S should be in [1 : q-1] while q is the group
order of the Secp384r1 curve.
These registers are located at ECC_base_address +
0x0000_0380 to 0x0000_03AC in big-endian representation.";
order of the Secp384r1 curve.";

default sw = rw;
default hw = rw;
Expand All @@ -286,14 +271,13 @@ addrmap ecc_reg {

/* ---- ECC Component Verify R Result ---- */
reg {
name = "ECC component verify R result register type definition";
desc = "12 32-bit registers storing the result of verifying operation.
name = "ECC VERIFY R";
desc = "ECC component verify R result register type definition
12 32-bit registers storing the result of verifying operation in big-endian representation.
Firmware is responsible for comparing the computed result with
the signature R, and if they are equal the signature is valid.
The verify R result should be in [1 : q-1] while q is the group
order of the Secp384r1 curve.
These registers are located at ECC_base_address +
0x0000_0400 to 0x0000_042C in big-endian representation.";
order of the Secp384r1 curve.";

default sw = r;
default hw = rw;
Expand All @@ -307,13 +291,12 @@ addrmap ecc_reg {

/* ---- ECC Component Input IV ---- */
reg {
name = "ECC component IV register type definition";
desc = "12 32-bit registers storing the 384-bit IV required
name = "ECC IV";
desc = "ECC component IV register type definition
12 32-bit registers storing the 384-bit IV required
for SCA countermeasures to randomize the inputs with no change
on the ECC outputs.
The IV can be any 384-bit value in [0 : 2^384-1].
These registers are located at ECC_base_address +
0x0000_0480 to 0x0000_04AC in big-endian representation.";
The IV can be any 384-bit value in [0 : 2^384-1].";

default sw = w;
default hw = r;
Expand Down
Loading

0 comments on commit e365602

Please sign in to comment.