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Merge dev-integrate -> main #299

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Dec 1, 2023
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b473793
Add test for Mailbox JTAG accesses with clock gating
robertszczepanski Aug 24, 2023
5608dfa
Merge pull request #238 from chipsalliance/main
calebofearth Oct 3, 2023
5eb4852
Merge pull request #197 from antmicro/rszc/jtag-cg-test
andreslagarcavilla Oct 25, 2023
b0a25ba
Merge pull request #286 from chipsalliance/main
calebofearth Nov 10, 2023
fa5e334
Merged PR 132462: [UVM] Fix for regression failure caused by soc_ifc …
calebofearth Nov 3, 2023
052c39e
Merged PR 133196: KV test content for coverage
upadhyayulakiran Nov 8, 2023
c3b817d
Merged PR 132944: UVM val firmware bug fix: solve a possible error ra…
calebofearth Nov 8, 2023
86d6ecf
Merged PR 133433: Add SV assertions to uvmf_caliptra_top testbench
calebofearth Nov 9, 2023
7c49c8c
Merged PR 133575: Remove top port TODO comments
calebofearth Nov 10, 2023
81a774b
Merge pull request #293 from chipsalliance/dev-msft-20231110
calebofearth Nov 13, 2023
1ce9ea6
Update expected mailbox rdptr value
mkurc-ant Nov 14, 2023
f12c8fe
Merge pull request #296 from chipsalliance/dev-msft
calebofearth Nov 14, 2023
4a89cff
Remove I3C interface placeholder comment (#300)
calebofearth Nov 15, 2023
674ac5f
Merge pull request #302 from antmicro/mkurc/fix-mailbox-test
mcockrell-google Nov 16, 2023
986b12a
Remove support for JTAG read IDCODE instruction from VeeR TAP
mkurc-ant Nov 14, 2023
cf4903d
Remove expected IDCODE from OpenOCD config
mkurc-ant Nov 14, 2023
7589fe4
Merge pull request #298 from antmicro/mkurc/remove-idcode
kgugala Nov 21, 2023
eeb0a57
[README] Update VCS steps (#308)
calebofearth Nov 22, 2023
63a40f0
Fix VCS invocation in Makefile so that DPI functions get compiled. (#…
mkurc-ant Nov 30, 2023
8173b30
Merged PR 133861: Filesystem merge from caliptra-rtl GitHub to MSFT i…
calebofearth Nov 14, 2023
3cc699b
Commit minor tweaks to sync infrastructure with MSFT internal repo (h…
calebofearth Nov 30, 2023
38d5fd7
Merged PR 134395: KV UVM fixes
upadhyayulakiran Nov 15, 2023
a622696
Merged PR 134100: Update synthesis script with FC commands
upadhyayulakiran Nov 15, 2023
340a3cd
Merged PR 134598: UVM regression fixes for soc_ifc deadlock and AHB s…
calebofearth Nov 17, 2023
c5884b8
Merged PR 134981: Update kv scan sequence
upadhyayulakiran Nov 18, 2023
15acd7b
Merged PR 136182: Fix ICCM ECC error not reported
calebofearth Nov 30, 2023
5bdfabd
Merge pull request #318 from chipsalliance/dev-msft-20231130
calebofearth Dec 1, 2023
c1ad07c
Merge pull request #319 from chipsalliance/dev-msft
calebofearth Dec 1, 2023
9082743
Merge pull request #310 from chipsalliance/dev-public
calebofearth Dec 1, 2023
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16 changes: 16 additions & 0 deletions .github/workflows/interactive-debugging.yml
Original file line number Diff line number Diff line change
Expand Up @@ -315,3 +315,19 @@ jobs:
${CALIPTRA_ROOT}/.github/scripts/openocd_test.sh \
-f board/caliptra-verilator-rst.cfg \
-f ${CALIPTRA_ROOT}/src/integration/test_suites/infinite_loop/peripheral_access.tcl

- name: Build Verilated simulation
run: |
export CALIPTRA_ROOT=$(pwd)
rm -rf run/*
make -C run -f ${CALIPTRA_ROOT}/tools/scripts/Makefile verilator-build TESTNAME=infinite_loop DEBUG_UNLOCKED=1 \
OBJCACHE="" CC=gcc CXX=g++ LINK=g++
make -C run -f ${CALIPTRA_ROOT}/tools/scripts/Makefile program.hex TESTNAME=infinite_loop

- name: Test JTAG access with clock gating
run: |
export CALIPTRA_ROOT=$(pwd)
cd run
${CALIPTRA_ROOT}/.github/scripts/openocd_test.sh \
-f board/caliptra-verilator.cfg \
-f ${CALIPTRA_ROOT}/src/integration/test_suites/infinite_loop/jtag_cg.tcl
77 changes: 68 additions & 9 deletions README.md
Original file line number Diff line number Diff line change
Expand Up @@ -41,8 +41,8 @@ Simulation:
- `2022.3`

Synthesis:
- Synopsys DC
- `Version 2020.09-SP1`
- Synopsys Fusion Compiler
- `Version 2022.12-SP3`

GCC:
- RISCV Toolchain for generating memory initialization files
Expand All @@ -55,7 +55,7 @@ Other:
- Playbook (Microsoft Internal workflow management tool)

### **RISCV Toolchain installation** ###
Note that there is significant configurability when installing the RISCV toolchain.
There is significant configurability when installing the RISCV toolchain.
These instructions may be used to create a RISCV installation that will be compatible
with the provided Makefile for compiling test C programs.

Expand All @@ -74,7 +74,7 @@ Required for simulation:<BR>
`CALIPTRA_ROOT`: Defines the absolute path to the Project repository root (called "Caliptra" or "caliptra-rtl"). Recommended to define as `${CALIPTRA_WORKSPACE}/Caliptra`.<BR>

Required for Firmware (i.e. Test suites) makefile:<BR>
`TESTNAME`: Contains the name of one of the tests listed inside the `src/integration/test_suites` folder<BR>
`TESTNAME`: Contains the name of one of the tests listed inside the `src/integration/test_suites` folder; only used for `caliptra_top_tb` tests<BR>

## **Repository Overview** ##
```
Expand Down Expand Up @@ -143,20 +143,28 @@ Verilog file lists are generated via VCS and included in the config directory fo

## **Simulation Flow** ##

### VCS Steps: ###
### Caliptra Top VCS Steps: ###
1. Setup tools, add to PATH (ensure riscv64-unknown-elf-gcc is also available)
2. Define all environment variables above
- For the initial test run after downloading repository, `iccm_lock` is recommended for TESTNAME
- See [Regression Tests](#Regression-Tests) for information about available tests.
3. Create a run folder for build outputs (and cd to it)
4. [OPTIONAL] By default, this run flow will use the riscv64 toolchain to compile test firmware (according to TESTNAME) into program.hex, iccm.hex, dccm.hex, and mailbox.hex. As a first pass, integrators may alternatively use the pre-built hexfiles for convenience (available for `iccm_lock` test). To do this, copy `iccm_lock.hex` to the run directory and rename to `program.hex`. `dccm.hex` should also be copied to the run directory, as-is. Use `touch iccm.hex mailbox.hex` to create empty hex files, as these are unnecessary for `iccm_lock` test.
4. [OPTIONAL] By default, this run flow will use the riscv64 toolchain to compile test firmware (according to TESTNAME) into program.hex, iccm.hex, dccm.hex, and mailbox.hex. As a first pass, integrators may alternatively use the pre-built hexfiles for convenience (available for [iccm_lock](src/integration/test_suites/iccm_lock) test). To do this, copy [iccm_lock.hex](src/integration/test_suites/iccm_lock/iccm_lock.hex) to the run directory and rename to `program.hex`. [dccm.hex](src/integration/test_suites/iccm_lock/iccm_lock.hex) should also be copied to the run directory, as-is. Use `touch iccm.hex mailbox.hex` to create empty hex files, as these are unnecessary for `iccm_lock` test.
5. Invoke `${CALIPTRA_ROOT}/tools/scripts/Makefile` with target 'program.hex' to produce SRAM initialization files from the firmware found in `src/integration/test_suites/${TESTNAME}`
- E.g.: `make -f ${CALIPTRA_ROOT}/tools/scripts/Makefile program.hex`
- NOTE: TESTNAME may also be overridden in the makefile command line invocation, e.g. `make -f ${CALIPTRA_ROOT}/tools/scripts/Makefile TESTNAME=iccm_lock program.hex`
6. Compile complete project using `src/integration/config/caliptra_top_tb.vf` as a compilation target in VCS. When running the `vcs` command to generate simv, users should ensure that `caliptra_top_tb` is explicitly specified as the top-level component in their command to ensure this is the sole "top" that gets simulated.
7. Simulate project with `caliptra_top_tb` as the top target
7. Copy the test generator scripts to the run output directory:
- [src/ecc/tb/ecdsa_secp384r1.exe](src/ecc/tb/ecdsa_secp384r1.exe)
* Necessary for [randomized_pcr_signing](src/integration/test_suites/randomized_pcr_signing)
* OPTIONAL otherwise
- [src/doe/tb/doe_test_gen.py](src/doe/tb/doe_test_gen.py)
* Allows use of randomized secret field inputs during testing.
* Required when using the `+RAND_DOE_VALUES` plusarg during simulation
* Also required for several smoke tests that require randomized DOE IV, such as smoke_test_doe_scan, smoke_test_doe_rand, smoke_test_doe_cg
8. Simulate project with `caliptra_top_tb` as the top target

### Verilator Steps: ###
### Caliptra Top Verilator Steps: ###
1. Setup tools, add to PATH (ensure Verilator, GCC, and riscv64-unknown-elf-gcc are available)
2. Define all environment variables above
- For the initial test run after downloading repository, `iccm_lock` is recommended for TESTNAME
Expand All @@ -178,6 +186,18 @@ Verilog file lists are generated via VCS and included in the config directory fo
3. NOTE: The script automatically creates run output folders at `${CALIPTRA_WORKSPACE}/scratch/$USER/verilator/<timestamp>/<testname>` for each test run
4. NOTE: The output folder is populated with a run log that reports the run results and pass/fail status

### Unit Test VCS Steps: ###
1. Setup tools, add to PATH
1. Define all environment variables above
1. Create a run folder for build outputs (and cd to it)
1. Compile complete project using `src/<block>/config/<name>_tb.vf` as a compilation target in VCS. When running the `vcs` command to generate simv, users should ensure that `<name>_tb` is explicitly specified as the top-level component in their command to ensure this is the sole "top" that gets simulated.
1. Copy the test generator scripts or test vectors to the run output directory:
- [src/ecc/tb/test_vectors/mm_test_vectors\*.hex](src/ecc/tb/test_vectors)
* Necessary for [ecc_montgomerymultiplier_tb](src/ecc/tb/ecc_montgomerymultiplier_tb.sv)
- [src/sha256/tb/sha256_test_gen.py](src/sha256/tb/sha256_test_gen.py)
* Necessary for [sha256_random_test](src/sha256/tb/sha256_random_test.sv)
1. Simulate project with `<name>_tb` as the top target

### UVM Testbench Steps for `caliptra_top`: <BR>

**Description**:<BR>
Expand All @@ -195,15 +215,54 @@ Steps:<BR>
1. Compile the UVMF wrapper for APB/AHB in Caliptra/src/libs/uvmf
1. Compile the `verification_ip` provided for `soc_ifc` found in `Caliptra/src/soc_ifc/uvmf_soc_ifc`
1. Compile the `caliptra_top` testbench found in `Caliptra/src/integration/uvmf_caliptra_top`
1. `Caliptra/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv` is the top-level TB wrapper for the system
1. ALL compilation steps may be completed by using the file-list found at `src/integration/uvmf_caliptra_top/config/uvmf_caliptra_top.vf`
1. NOTE: `Caliptra/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv` is the top-level TB wrapper for the system
1. Compile the validation firmware (as described in [Regression Tests](#Regression-Tests)) that will run on Caliptra's embedded RISC-V core
- The expected output products are `program.hex`, `caliptra_fmc.hex`, `caliptra_rt.hex` and must be placed in the simulation run directory
- `make -f ${CALIPTRA_ROOT}/tools/scripts/Makefile TESTNAME=caliptra_top program.hex`
- `make -f ${CALIPTRA_ROOT}/tools/scripts/Makefile TESTNAME=caliptra_fmc caliptra_fmc.hex`
- `make -f ${CALIPTRA_ROOT}/tools/scripts/Makefile TESTNAME=caliptra_rt caliptra_rt.hex`
1. Copy the test vectors to the run output directory:
- [src/sha512/tb/vectors/SHA\*.rsp](src/sha512/tb/vectors/)
* Required for SHA512 UVM unittest
1. Select a test to run from the set of tests in `Caliptra/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src`
1. Provide `+UVM_TESTNAME=<test>` argument to simulation

### UVM Unit Test Steps: <BR>

**Description**:<BR>
The UVM Framework generation tool was used to create the baseline UVM testbench for verification of each IP component inside Caliptra. The following IP blocks have supported UVM testbenches:
- [ECC](src/ecc/uvmf_ecc)
- [HMAC](src/hmac/uvmf_2022)
- [SHA512](src/sha512/uvmf_sha512)
- [KeyVault](src/keyvault/uvmf_kv)
- [PCRVault](src/pcrvault/uvmf_pv)
- [SOC_IFC](src/soc_ifc/uvmf_soc_ifc)

**Prerequisites**:<BR>
- QVIP 2021.2.1 for Mentor Graphics (provides the AHB/APB VIP)
- UVM 1.1d installation
- Mentor Graphics UVM-Framework installation

Steps:<BR>
1. Compile UVM 1.1d library
1. Compile the AHB/APB QVIP source
1. Compile the Mentor Graphics UVM-Frameworks base library
1. Compile the UVMF wrapper for APB/AHB in Caliptra/src/libs/uvmf
1. Compile the `verification_ip` provided for the target testbench
1. ALL compilation steps may be completed by using the file-list found at `src/<block>/uvmf_<name>/config/<name>.vf`
1. NOTE: `Caliptra/src/<block>/uvmf_<name>/uvmf_template_output/project_benches/<block>/tb/testbench/hdl_top.sv` is the top-level TB wrapper for the system
1. Copy the test generator scripts to the run output directory:
- [src/ecc/tb/ecdsa_secp384r1.exe](src/ecc/tb/ecdsa_secp384r1.exe)
* Necessary for ECC unittest
- [src/hmac/tb/test_gen.py](src/hmac/tb/test_gen.py)
* Required for uvmf_hmac unittest
- [src/sha512/tb/vectors/SHA\*.rsp](src/sha512/tb/vectors/)
* Required for SHA512 UVM unittest
1. Select a test to run from the set of tests in `Caliptra/src/<block>/uvmf_<name>/uvmf_template_output/project_benches/<block>/tb/tests/src`
1. Provide `+UVM_TESTNAME=<test>` argument to simulation


## **Regression Tests** ##

### Standalone SystemVerilog Testbench Regression ###
Expand Down
1 change: 0 additions & 1 deletion src/aes/config/aes.vf
Original file line number Diff line number Diff line change
@@ -1,4 +1,3 @@

+incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl
+incdir+${CALIPTRA_ROOT}/src/integration/rtl
+incdir+${CALIPTRA_ROOT}/src/libs/rtl
Expand Down
1 change: 0 additions & 1 deletion src/aes/config/aes_pkg.vf
Original file line number Diff line number Diff line change
@@ -1,4 +1,3 @@

+incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl
+incdir+${CALIPTRA_ROOT}/src/integration/rtl
+incdir+${CALIPTRA_ROOT}/src/libs/rtl
Expand Down
1 change: 0 additions & 1 deletion src/ahb_lite_bus/config/ahb_lite_bus.vf
Original file line number Diff line number Diff line change
@@ -1,4 +1,3 @@

+incdir+${CALIPTRA_ROOT}/src/integration/rtl
+incdir+${CALIPTRA_ROOT}/src/libs/rtl
+incdir+${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl
Expand Down
1 change: 0 additions & 1 deletion src/caliptra_prim/config/caliptra_prim.vf
Original file line number Diff line number Diff line change
@@ -1,4 +1,3 @@

+incdir+${CALIPTRA_ROOT}/src/integration/rtl
+incdir+${CALIPTRA_ROOT}/src/libs/rtl
+incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl
Expand Down
1 change: 0 additions & 1 deletion src/caliptra_prim/config/caliptra_prim_pkg.vf
Original file line number Diff line number Diff line change
@@ -1,4 +1,3 @@

+incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl
${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv
${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv
Expand Down
1 change: 0 additions & 1 deletion src/caliptra_prim_generic/config/caliptra_prim_generic.vf
Original file line number Diff line number Diff line change
@@ -1,4 +1,3 @@

+incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl
${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv
${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv
Expand Down
2 changes: 0 additions & 2 deletions src/csrng/config/csrng.vf
Original file line number Diff line number Diff line change
@@ -1,4 +1,3 @@

+incdir+${CALIPTRA_ROOT}/src/integration/rtl
+incdir+${CALIPTRA_ROOT}/src/libs/rtl
+incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl
Expand Down Expand Up @@ -103,4 +102,3 @@ ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_block_encrypt.sv
${CALIPTRA_ROOT}/src/csrng/rtl/csrng_state_db.sv
${CALIPTRA_ROOT}/src/csrng/rtl/csrng_cmd_stage.sv
${CALIPTRA_ROOT}/src/csrng/rtl/csrng.sv
${CALIPTRA_ROOT}/src/csrng/tb/csrng_tb.sv
1 change: 0 additions & 1 deletion src/csrng/config/csrng_pkg.vf
Original file line number Diff line number Diff line change
@@ -1,4 +1,3 @@

+incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl
+incdir+${CALIPTRA_ROOT}/src/csrng/rtl
${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv
Expand Down
1 change: 0 additions & 1 deletion src/csrng/config/csrng_tb.vf
Original file line number Diff line number Diff line change
@@ -1,4 +1,3 @@

+incdir+${CALIPTRA_ROOT}/src/integration/rtl
+incdir+${CALIPTRA_ROOT}/src/libs/rtl
+incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl
Expand Down
1 change: 0 additions & 1 deletion src/datavault/config/datavault.vf
Original file line number Diff line number Diff line change
@@ -1,4 +1,3 @@

+incdir+${CALIPTRA_ROOT}/src/integration/rtl
+incdir+${CALIPTRA_ROOT}/src/libs/rtl
+incdir+${CALIPTRA_ROOT}/src/datavault/rtl
Expand Down
1 change: 0 additions & 1 deletion src/datavault/config/dv_defines_pkg.vf
Original file line number Diff line number Diff line change
@@ -1,4 +1,3 @@

+incdir+${CALIPTRA_ROOT}/src/datavault/rtl
${CALIPTRA_ROOT}/src/datavault/rtl/dv_defines_pkg.sv
${CALIPTRA_ROOT}/src/datavault/rtl/dv_defines_pkg.sv
1 change: 0 additions & 1 deletion src/datavault/config/dv_uvm_pkg.vf
Original file line number Diff line number Diff line change
@@ -1,3 +1,2 @@

+incdir+${CALIPTRA_ROOT}/src/datavault/rtl
${CALIPTRA_ROOT}/src/datavault/rtl/dv_reg_uvm.sv
1 change: 0 additions & 1 deletion src/doe/config/doe_cbc_tb.vf
Original file line number Diff line number Diff line change
@@ -1,4 +1,3 @@

+incdir+${CALIPTRA_ROOT}/src/integration/rtl
+incdir+${CALIPTRA_ROOT}/src/libs/rtl
+incdir+${CALIPTRA_ROOT}/src/keyvault/rtl
Expand Down
1 change: 0 additions & 1 deletion src/doe/config/doe_core_cbc_tb.vf
Original file line number Diff line number Diff line change
@@ -1,4 +1,3 @@

+incdir+${CALIPTRA_ROOT}/src/integration/rtl
+incdir+${CALIPTRA_ROOT}/src/libs/rtl
+incdir+${CALIPTRA_ROOT}/src/keyvault/rtl
Expand Down
1 change: 0 additions & 1 deletion src/doe/config/doe_ctrl.vf
Original file line number Diff line number Diff line change
@@ -1,4 +1,3 @@

+incdir+${CALIPTRA_ROOT}/src/integration/rtl
+incdir+${CALIPTRA_ROOT}/src/libs/rtl
+incdir+${CALIPTRA_ROOT}/src/keyvault/rtl
Expand Down
1 change: 0 additions & 1 deletion src/doe/config/doe_defines_pkg.vf
Original file line number Diff line number Diff line change
@@ -1,4 +1,3 @@

+incdir+${CALIPTRA_ROOT}/src/doe/rtl
${CALIPTRA_ROOT}/src/doe/rtl/doe_defines_pkg.sv
${CALIPTRA_ROOT}/src/doe/rtl/doe_defines_pkg.sv
1 change: 0 additions & 1 deletion src/ecc/config/ecc_montgomerymultiplier_tb.vf
Original file line number Diff line number Diff line change
@@ -1,4 +1,3 @@

+incdir+${CALIPTRA_ROOT}/src/integration/rtl
+incdir+${CALIPTRA_ROOT}/src/libs/rtl
+incdir+${CALIPTRA_ROOT}/src/keyvault/rtl
Expand Down
1 change: 0 additions & 1 deletion src/ecc/config/ecc_top.vf
Original file line number Diff line number Diff line change
@@ -1,4 +1,3 @@

+incdir+${CALIPTRA_ROOT}/src/integration/rtl
+incdir+${CALIPTRA_ROOT}/src/libs/rtl
+incdir+${CALIPTRA_ROOT}/src/keyvault/rtl
Expand Down
1 change: 0 additions & 1 deletion src/ecc/config/ecc_top_tb.vf
Original file line number Diff line number Diff line change
@@ -1,4 +1,3 @@

+incdir+${CALIPTRA_ROOT}/src/integration/rtl
+incdir+${CALIPTRA_ROOT}/src/libs/rtl
+incdir+${CALIPTRA_ROOT}/src/keyvault/rtl
Expand Down
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