Merge dev-integrate -> main

.github/scripts/build_tests_matrix.py

@@ -1,4 +1,18 @@
 #!/usr/bin/env python3
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
 import os
 import yaml
 

.github/scripts/gdb_test.sh

@@ -1,4 +1,17 @@
 #!/bin/bash
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
 #
 # This script runs Verilator RTL simulation and OpenOCD in background, invokes
 # the supplied test command and shuts everything down.

.github/scripts/openocd_test.sh

@@ -1,4 +1,17 @@
 #!/bin/bash
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
 #
 # This script runs Verilator RTL simulation in background and invokes OpenOCD
 # to perform JTAG access test

.github/scripts/utils.sh

@@ -1,4 +1,18 @@
 #!/bin/bash
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
 
 # Colors
 COLOR_OFF='\033[0m'

README.md

@@ -208,7 +208,12 @@ The UVM Framework generation tool was used to create the baseline UVM testbench
 - UVM 1.1d installation
 - Mentor Graphics UVM-Framework installation
 
-Steps:<BR>
+**Environment Variables**:<BR>
+`UVM_HOME`: Filesystem path to the parent directory containing SystemVerilog source code for the UVM library of the desired version.
+`UVMF_HOME`: Filesystem path to the parent directory containing source code (uvmf_base_pkg) for the UVM Frameworks library, a tool available from Mentor Graphics for generating baseline UVM projects.
+`QUESTA_MVC_HOME`: Filesystem path to the parent directory containing source code for Mentor Graphics QVIP, the verification library from which AHB/APB UVM agents are pulled in the Caliptra UVM environment.
+
+**Steps:**<BR>
 1. Compile UVM 1.1d library
 1. Compile the AHB/APB QVIP source
 1. Compile the Mentor Graphics UVM-Frameworks base library
@@ -244,7 +249,7 @@ The UVM Framework generation tool was used to create the baseline UVM testbench
 - UVM 1.1d installation
 - Mentor Graphics UVM-Framework installation
 
-Steps:<BR>
+**Steps:**<BR>
 1. Compile UVM 1.1d library
 1. Compile the AHB/APB QVIP source
 1. Compile the Mentor Graphics UVM-Frameworks base library

src/ahb_lite_bus/config/compile.yml

@@ -15,5 +15,5 @@ targets:
   rtl_lint:
     directories: []
     waiver_files: 
-    - $COMPILE_ROOT/config/design_lint/ahb_lite_bus/sglint_waivers
+    - $MSFT_REPO_ROOT/src/ahb_lite_bus/config/design_lint/ahb_lite_bus/sglint_waivers
 

src/caliptra_prim/config/caliptra_prim_pkg.vf

@@ -6,4 +6,3 @@ ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv
 ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv
-${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv

src/datavault/config/compile.yml

@@ -36,7 +36,7 @@ targets:
   rtl_lint:
     directories: []
     waiver_files:
-      - $COMPILE_ROOT/config/design_lint/datavault/sglint_waivers
+      - $MSFT_REPO_ROOT/src/datavault/config/design_lint/datavault/sglint_waivers
     black_box:
       - dv_reg
 global:

src/doe/config/compile.yml

@@ -38,7 +38,7 @@ targets:
   rtl_lint:
     directories: []
     waiver_files:
-      - $COMPILE_ROOT/config/design_lint/doe_ctrl/sglint_waivers
+      - $MSFT_REPO_ROOT/src/doe/config/design_lint/doe_ctrl/sglint_waivers
     black_box:
       - doe_reg
 ---

src/ecc/config/compile.yml

@@ -40,7 +40,7 @@ targets:
   rtl_lint:
     directories: []
     waiver_files:
-      - $COMPILE_ROOT/config/design_lint/ecc_top/sglint_waivers
+      - $MSFT_REPO_ROOT/src/ecc/config/design_lint/ecc_top/sglint_waivers
     black_box:
       - ecc_reg
 ---

src/hmac/config/compile.yml

@@ -19,7 +19,7 @@ targets:
   rtl_lint:
     directories: []
     waiver_files: 
-      - $COMPILE_ROOT/config/design_lint/hmac_ctrl/sglint_waivers
+      - $MSFT_REPO_ROOT/src/hmac/config/design_lint/hmac_ctrl/sglint_waivers
     black_box:
       - hmac_reg
 ---

src/integration/asserts/caliptra_top_sva.sv

@@ -24,22 +24,29 @@
 `else
 `define CPTRA_TB_TOP_NAME caliptra_top_tb
 `endif
-`define CPTRA_TOP_PATH  `CPTRA_TB_TOP_NAME.caliptra_top_dut
-`define KEYVAULT_PATH   `CPTRA_TOP_PATH.key_vault1
-`define DOE_INST_PATH   `CPTRA_TOP_PATH.doe.doe_inst
-`define DOE_PATH        `DOE_INST_PATH.doe_fsm1
-`define DOE_REG_PATH    `DOE_INST_PATH.i_doe_reg
-`define SERVICES_PATH   `CPTRA_TB_TOP_NAME.tb_services_i
-`define SHA512_PATH     `CPTRA_TOP_PATH.sha512.sha512_inst
-`define HMAC_PATH       `CPTRA_TOP_PATH.hmac.hmac_inst
-`define ECC_PATH        `CPTRA_TOP_PATH.ecc_top1.ecc_dsa_ctrl_i
-`define ECC_REG_PATH    `CPTRA_TOP_PATH.ecc_top1.ecc_reg1
-`define SHA256_PATH     `CPTRA_TOP_PATH.sha256.sha256_inst
-`define SHA512_MASKED_PATH `CPTRA_TOP_PATH.ecc_top1.ecc_dsa_ctrl_i.ecc_hmac_drbg_interface_i.hmac_drbg_i.HMAC_K.u_sha512_core_h1
-`define SOC_IFC_TOP_PATH   `CPTRA_TOP_PATH.soc_ifc_top1
-`define WDT_PATH        `SOC_IFC_TOP_PATH.i_wdt
+`define CPTRA_TOP_PATH      `CPTRA_TB_TOP_NAME.caliptra_top_dut
+`define KEYVAULT_PATH       `CPTRA_TOP_PATH.key_vault1
+`define KEYVAULT_REG_PATH   `KEYVAULT_PATH.kv_reg1
+`define PCRVAULT_PATH       `CPTRA_TOP_PATH.pcr_vault1
+`define PCRVAULT_REG_PATH   `PCRVAULT_PATH.pv_reg1
+`define DATA_VAULT_PATH     `CPTRA_TOP_PATH.data_vault1
+`define DATA_VAULT_REG_PATH `DATA_VAULT_PATH.dv_reg1
+`define DOE_INST_PATH       `CPTRA_TOP_PATH.doe.doe_inst
+`define DOE_PATH            `DOE_INST_PATH.doe_fsm1
+`define DOE_REG_PATH        `DOE_INST_PATH.i_doe_reg
+`define SERVICES_PATH       `CPTRA_TB_TOP_NAME.tb_services_i
+`define SHA512_PATH         `CPTRA_TOP_PATH.sha512.sha512_inst
+`define HMAC_PATH           `CPTRA_TOP_PATH.hmac.hmac_inst
+`define HMAC_REG_PATH       `HMAC_PATH.i_hmac_reg
+`define ECC_PATH            `CPTRA_TOP_PATH.ecc_top1.ecc_dsa_ctrl_i
+`define ECC_REG_PATH        `CPTRA_TOP_PATH.ecc_top1.ecc_reg1
+`define SHA256_PATH         `CPTRA_TOP_PATH.sha256.sha256_inst
+`define SHA512_MASKED_PATH  `CPTRA_TOP_PATH.ecc_top1.ecc_dsa_ctrl_i.ecc_hmac_drbg_interface_i.hmac_drbg_i.HMAC_K.u_sha512_core_h1
+`define SOC_IFC_TOP_PATH    `CPTRA_TOP_PATH.soc_ifc_top1
+`define WDT_PATH            `SOC_IFC_TOP_PATH.i_wdt
 
 `define SVA_RDC_CLK `CPTRA_TOP_PATH.rdc_clk_cg
+`define CPTRA_FW_UPD_RST_WINDOW `SOC_IFC_TOP_PATH.i_soc_ifc_boot_fsm.fw_update_rst_window
 `ifdef UVMF_CALIPTRA_TOP
   `define SVA_CLK `CPTRA_TB_TOP_NAME.clk
   `define SVA_RST `CPTRA_TB_TOP_NAME.soc_ifc_subenv_soc_ifc_ctrl_agent_bus.cptra_rst_b
@@ -552,5 +559,25 @@ module caliptra_top_sva
                                       `ECC_PATH.ecc_arith_unit_i.ecc_instr_s.opcode.mult_we |-> (`ECC_PATH.ecc_arith_unit_i.mult_res_s < `ECC_PATH.ecc_arith_unit_i.adder_prime)
                                       )
                           else $display("SVA ERROR: ECC multiplier result is not valid!"); 
-endmodule
 
+  // Bus IDLE on Firmware Update Reset
+  fw_upd_rst_doe_idle:     assert property (@(posedge `SVA_RDC_CLK) `CPTRA_FW_UPD_RST_WINDOW |-> !`DOE_REG_PATH.s_cpuif_req)
+                           else $display("SVA ERROR: DOE bus not idle after Firmware Update Reset!");
+  fw_upd_rst_ecc_idle:     assert property (@(posedge `SVA_RDC_CLK) `CPTRA_FW_UPD_RST_WINDOW |-> !`ECC_REG_PATH.s_cpuif_req)
+                           else $display("SVA ERROR: ECC bus not idle after Firmware Update Reset!");
+  fw_upd_rst_hmac_idle:    assert property (@(posedge `SVA_RDC_CLK) `CPTRA_FW_UPD_RST_WINDOW |-> !`HMAC_REG_PATH.s_cpuif_req)
+                           else $display("SVA ERROR: HMAC bus not idle after Firmware Update Reset!");
+  fw_upd_rst_kv_idle:      assert property (@(posedge `SVA_RDC_CLK) `CPTRA_FW_UPD_RST_WINDOW |-> !`KEYVAULT_REG_PATH.s_cpuif_req)
+                           else $display("SVA ERROR: Key Vault bus not idle after Firmware Update Reset!");
+  fw_upd_rst_pv_idle:      assert property (@(posedge `SVA_RDC_CLK) `CPTRA_FW_UPD_RST_WINDOW |-> !`PCRVAULT_REG_PATH.s_cpuif_req)
+                           else $display("SVA ERROR: PCR Vault bus not idle after Firmware Update Reset!");
+  fw_upd_rst_dv_idle:      assert property (@(posedge `SVA_RDC_CLK) `CPTRA_FW_UPD_RST_WINDOW |-> !`DATA_VAULT_REG_PATH.s_cpuif_req)
+                           else $display("SVA ERROR: Data Vault bus not idle after Firmware Update Reset!");
+  fw_upd_rst_sha256_idle:  assert property (@(posedge `SVA_RDC_CLK) `CPTRA_FW_UPD_RST_WINDOW |-> !`SHA256_PATH.i_sha256_reg.s_cpuif_req)
+                           else $display("SVA ERROR: SHA256 bus not idle after Firmware Update Reset!");
+  fw_upd_rst_sha512_idle:  assert property (@(posedge `SVA_RDC_CLK) `CPTRA_FW_UPD_RST_WINDOW |-> !`SHA512_PATH.i_sha512_reg.s_cpuif_req)
+                           else $display("SVA ERROR: SHA512 bus not idle after Firmware Update Reset!");
+  fw_upd_rst_soc_ifc_idle: assert property (@(posedge `SVA_RDC_CLK) `CPTRA_FW_UPD_RST_WINDOW |-> !`SOC_IFC_TOP_PATH.i_ahb_slv_sif_soc_ifc.dv)
+                           else $display("SVA ERROR: SOC_IFC bus not idle after Firmware Update Reset!");
+
+endmodule

src/integration/config/compile.yml

@@ -45,7 +45,7 @@ targets:
     tops: [caliptra_top]
   rtl_lint:
     waiver_files:
-      - $COMPILE_ROOT/config/design_lint/sglint_waivers
+      - $MSFT_REPO_ROOT/src/integration/config/design_lint/sglint_waivers
     black_box:
       - el2_veer_wrapper
   cdc:
@@ -109,7 +109,7 @@ targets:
       - $COMPILE_ROOT/tb/caliptra_top_tb.sv
     tops: [caliptra_top_tb]
   sim:
-    pre_exec: '$MSFT_TOOLS/scripts/run_test_makefile && echo "[PRE-EXEC] Copying ECC vector generator to ${pwd}" && cp $COMPILE_ROOT/../ecc/tb/ecdsa_secp384r1.exe . 
+    pre_exec: '$MSFT_SCRIPTS_DIR/run_test_makefile && echo "[PRE-EXEC] Copying ECC vector generator to ${pwd}" && cp $COMPILE_ROOT/../ecc/tb/ecdsa_secp384r1.exe . 
                 && echo "[PRE-EXEC] Copying DOE vector generator to ${pwd}" && cp $COMPILE_ROOT/../doe/tb/doe_test_gen.py .'
 global:
   tool:

src/integration/stimulus/L0_regression.yml

@@ -9,7 +9,7 @@ contents:
         #add back for aes
         #- ../test_suites/smoke_test_aes/smoke_test_aes.yml
         - ../test_suites/smoke_test_mbox/smoke_test_mbox.yml
-        #- ../test_suites/smoke_test_mbox_cg/smoke_test_mbox_cg.yml
+        - ../test_suites/smoke_test_mbox_cg/smoke_test_mbox_cg.yml
         - ../test_suites/smoke_test_sha512/smoke_test_sha512.yml
         - ../test_suites/smoke_test_sha256/smoke_test_sha256.yml
         - ../test_suites/smoke_test_sha_accel/smoke_test_sha_accel.yml
@@ -37,7 +37,7 @@ contents:
         - ../test_suites/smoke_test_kv_hmac_flow/smoke_test_kv_hmac_flow.yml
         - ../test_suites/smoke_test_kv_sha512_flow/smoke_test_kv_sha512_flow.yml
         - ../test_suites/smoke_test_kv_crypto_flow/smoke_test_kv_crypto_flow.yml
-        #- ../test_suites/smoke_test_kv_cg/smoke_test_kv_cg.yml
+        - ../test_suites/smoke_test_kv_cg/smoke_test_kv_cg.yml
         - ../test_suites/pv_hash_and_sign/pv_hash_and_sign.yml
         - ../test_suites/smoke_test_pcr_signing/smoke_test_pcr_signing.yml
         - ../test_suites/smoke_test_fw_kv_backtoback_hmac/smoke_test_fw_kv_backtoback_hmac.yml
@@ -47,7 +47,7 @@ contents:
         - ../test_suites/smoke_test_doe_rand/smoke_test_doe_rand.yml
         - ../test_suites/smoke_test_doe_scan/smoke_test_doe_scan.yml
         - ../test_suites/smoke_test_zeroize_crypto/smoke_test_zeroize_crypto.yml
-        #- ../test_suites/smoke_test_doe_cg/smoke_test_doe_cg.yml
+        - ../test_suites/smoke_test_doe_cg/smoke_test_doe_cg.yml
         # data vault tests
         - ../test_suites/smoke_test_datavault_basic/smoke_test_datavault_basic.yml
         - ../test_suites/smoke_test_datavault_reset/smoke_test_datavault_reset.yml

src/integration/stimulus/testsuites/uvmf_caliptra_top_nightly_directed_regression.yml

@@ -7,8 +7,8 @@ contents:
       path: ""
       config:
         params:
-          # 12 hours
-          timeout: 720
+          # 24 hours
+          timeout: 1440
       weight: 100
       generations: 1
       formats: 

src/integration/tb/caliptra_top_tb_services.sv

@@ -1059,7 +1059,7 @@ endgenerate //IV_NO
         wb_valid  <= `DEC.dec_i0_wen_r;
         wb_dest   <= `DEC.dec_i0_waddr_r;
         wb_data   <= `DEC.dec_i0_wdata_r;
-        if (caliptra_top_dut.trace_rv_i_valid_ip && !$test$plusargs("CLP_REGRESSION")) begin
+        if (caliptra_top_dut.trace_rv_i_valid_ip && $test$plusargs("CLP_BUS_LOGS")) begin
 
            $fwrite(tp,"%b,%h,%h,%0h,%0h,3,%b,%h,%h,%b\n", caliptra_top_dut.trace_rv_i_valid_ip, 0, caliptra_top_dut.trace_rv_i_address_ip,
                   0, caliptra_top_dut.trace_rv_i_insn_ip,caliptra_top_dut.trace_rv_i_exception_ip,caliptra_top_dut.trace_rv_i_ecause_ip,
@@ -1074,18 +1074,18 @@ endgenerate //IV_NO
                    );
         end
         if(`DEC.dec_nonblock_load_wen) begin
-            if (!$test$plusargs("CLP_REGRESSION")) $fwrite (el, "%10d : %32s=%h ; nbL\n", cycleCnt, abi_reg[`DEC.dec_nonblock_load_waddr], `DEC.lsu_nonblock_load_data);
+            if ($test$plusargs("CLP_BUS_LOGS")) $fwrite (el, "%10d : %32s=%h ; nbL\n", cycleCnt, abi_reg[`DEC.dec_nonblock_load_waddr], `DEC.lsu_nonblock_load_data);
             caliptra_top_tb_services.gpr[0][`DEC.dec_nonblock_load_waddr] = `DEC.lsu_nonblock_load_data;
         end
         if(`DEC.exu_div_wren) begin
-            if (!$test$plusargs("CLP_REGRESSION")) $fwrite (el, "%10d : %32s=%h ; nbD\n", cycleCnt, abi_reg[`DEC.div_waddr_wb], `DEC.exu_div_result);
+            if ($test$plusargs("CLP_BUS_LOGS")) $fwrite (el, "%10d : %32s=%h ; nbD\n", cycleCnt, abi_reg[`DEC.div_waddr_wb], `DEC.exu_div_result);
             caliptra_top_tb_services.gpr[0][`DEC.div_waddr_wb] = `DEC.exu_div_result;
         end
     end
 
     // IFU Initiator monitor
     always @(posedge clk) begin
-        if (!$test$plusargs("CLP_REGRESSION"))
+        if (!$test$plusargs("CLP_BUS_LOGS"))
         $fstrobe(ifu_p, "%10d : 0x%0h %h %b %h %h %h %b 0x%08h_%08h %b %b\n", cycleCnt, 
                         caliptra_top_dut.ic_haddr, caliptra_top_dut.ic_hburst, caliptra_top_dut.ic_hmastlock, 
                         caliptra_top_dut.ic_hprot, caliptra_top_dut.ic_hsize, caliptra_top_dut.ic_htrans, 
@@ -1095,7 +1095,7 @@ endgenerate //IV_NO
 
     // LSU Initiator monitor
     always @(posedge clk) begin
-        if (!$test$plusargs("CLP_REGRESSION"))
+        if ($test$plusargs("CLP_BUS_LOGS"))
         $fstrobe(lsu_p, "%10d : 0x%0h %h %h %b 0x%08h_%08h 0x%08h_%08h %b %b\n", cycleCnt, 
                         caliptra_top_dut.initiator_inst.haddr, caliptra_top_dut.initiator_inst.hsize, caliptra_top_dut.initiator_inst.htrans, 
                         caliptra_top_dut.initiator_inst.hwrite, caliptra_top_dut.initiator_inst.hrdata[63:32], caliptra_top_dut.initiator_inst.hrdata[31:0], 
@@ -1108,7 +1108,7 @@ endgenerate //IV_NO
     generate
         for (sl_i = 0; sl_i < `CALIPTRA_AHB_SLAVES_NUM; sl_i = sl_i + 1) begin: gen_responder_inf_monitor
             always @(posedge clk) begin
-                if (!$test$plusargs("CLP_REGRESSION"))
+                if ($test$plusargs("CLP_BUS_LOGS"))
                 $fstrobe(sl_p[sl_i], "%10d : 0x%0h %h %h %b 0x%08h_%08h 0x%08h_%08h %b %b %b %b\n", cycleCnt, 
                         caliptra_top_dut.responder_inst[sl_i].haddr, caliptra_top_dut.responder_inst[sl_i].hsize, caliptra_top_dut.responder_inst[sl_i].htrans, 
                         caliptra_top_dut.responder_inst[sl_i].hwrite, caliptra_top_dut.responder_inst[sl_i].hrdata[63:32], caliptra_top_dut.responder_inst[sl_i].hrdata[31:0], 
@@ -1167,13 +1167,13 @@ endgenerate //IV_NO
         if (!hex_file_is_empty) $readmemh("dccm.hex",     dummy_dccm_preloader.ram,0,32'h0001_FFFF);
         hex_file_is_empty = $system("test -s iccm.hex");
         if (!hex_file_is_empty) $readmemh("iccm.hex",     dummy_iccm_preloader.ram,0,32'h0001_FFFF);
-        if (!$test$plusargs("CLP_REGRESSION")) begin
+        if ($test$plusargs("CLP_BUS_LOGS")) begin
             tp = $fopen("trace_port.csv","w");
             el = $fopen("exec.log","w");
             ifu_p = $fopen("ifu_master_ahb_trace.log", "w");
             lsu_p = $fopen("lsu_master_ahb_trace.log", "w");
         end
-        if (!$test$plusargs("CLP_REGRESSION")) begin
+        if ($test$plusargs("CLP_BUS_LOGS")) begin
             $fwrite (el, "//   Cycle : #inst    0    pc    opcode    reg=value   ; mnemonic\n");
             $fwrite(ifu_p, "//   Cycle: ic_haddr     ic_hburst     ic_hmastlock     ic_hprot     ic_hsize     ic_htrans     ic_hwrite     ic_hrdata     ic_hwdata     ic_hready     ic_hresp\n");
             $fwrite(lsu_p, "//   Cycle: lsu_haddr     lsu_hsize     lsu_htrans     lsu_hwrite     lsu_hrdata     lsu_hwdata     lsu_hready     lsu_hresp\n");

src/integration/test_suites/smoke_test_clk_gating/smoke_test_clk_gating.yml

@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+---
+seed: 1
+testname: smoke_test_clk_gating