[rtl] l/s instruction issue must allcate by vrf.

chipsalliance · Jul 17, 2024 · 9fb2073 · 9fb2073
1 parent 4cf9ba4
commit 9fb2073
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Showing 3 changed files with 10 additions and 1 deletion.
diff --git a/t1/src/Lane.scala b/t1/src/Lane.scala
@@ -325,6 +325,9 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
     parameter.datapathWidth
   ))))
 
+  @public
+  val vrfAllocateIssue: Bool = IO(Output(Bool()))
+
   // TODO: remove
   dontTouch(writeBusPort)
 
@@ -1135,6 +1138,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
   vrf.instructionWriteReport.bits.state.wLaneLastReport := !laneRequest.valid
   vrf.instructionWriteReport.bits.state.wTopLastReport := !laneRequest.bits.decodeResult(Decoder.maskUnit)
   vrf.instructionWriteReport.bits.state.wLaneClear := false.B
+  vrfAllocateIssue := vrf.vrfAllocateIssue
 
   val elementSizeForOneRegister: Int = parameter.vLen / parameter.datapathWidth / parameter.laneNumber
   val nrMask: UInt = VecInit(Seq.tabulate(8){ i =>

diff --git a/t1/src/T1.scala b/t1/src/T1.scala
@@ -1632,6 +1632,7 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa
 
   /** for lsu instruction lsu is ready, for normal instructions, lanes are ready. */
   val executionReady: Bool = (!isLoadStoreType || lsu.request.ready) && (noOffsetReadLoadStore || allLaneReady)
+  val vrfAllocate: Bool = VecInit(laneVec.map(_.vrfAllocateIssue)).asUInt.andR
   // - ready to issue instruction
   // - for vi and vx type of gather, it need to access vs2 for one time, we read vs2 firstly in `gatherReadFinish`
   //   and convert it to mv instruction.
@@ -1640,7 +1641,7 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa
   //   we detect the hazard and decide should we issue this slide or
   //   issue the instruction after the slide which already in the slot.
   requestRegDequeue.ready := executionReady && slotReady && (!gatherNeedRead || gatherReadFinish) &&
-    instructionRAWReady && instructionIndexFree
+    instructionRAWReady && instructionIndexFree && vrfAllocate
 
   instructionToSlotOH := Mux(requestRegDequeue.fire, slotToEnqueue, 0.U)
 

diff --git a/t1/src/vrf/VRF.scala b/t1/src/vrf/VRF.scala
@@ -208,6 +208,9 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar
   @public
   val vrfReadyToStore: Bool = IO(Output(Bool()))
 
+  @public
+  val vrfAllocateIssue: Bool = IO(Output(Bool()))
+
   /** we can only chain LSU instructions, after [[LSU.writeQueueVec]] is cleared. */
   @public
   val loadDataInLSUWriteQueue: UInt = IO(Input(UInt(parameter.chainingSize.W)))
@@ -431,6 +434,7 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar
     recordFFO,
     0.U((parameter.chainingSize + 1).W)
   )
+  vrfAllocateIssue := freeRecord.orR && olderCheck
 
   val writePort: Seq[ValidIO[VRFWriteRequest]] = Seq(writePipe)
   val writeOH = writePort.map(p => UIntToOH((p.bits.vd ## p.bits.offset)(parameter.vrfOffsetBits + 3 - 1, 0)))