[rtl] fix source for SimpleAccessUnit.

chipsalliance · Jul 10, 2024 · c4c7f64 · c4c7f64
1 parent ac9db6b
commit c4c7f64
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/t1/src/lsu/LSU.scala b/t1/src/lsu/LSU.scala
@@ -396,8 +396,8 @@ class LSU(param: LSUParameter) extends Module {
   otherUnit.memReadResponse.bits.source := simpleSourceQueue.io.deq.bits
   simpleAccessPorts.r.ready := otherUnit.memReadResponse.ready
 
-  simpleSourceQueue.io.enq.valid := otherUnit.memReadResponse.valid && simpleAccessPorts.ar.ready
-  simpleSourceQueue.io.enq.bits := otherUnit.memReadResponse.bits.source
+  simpleSourceQueue.io.enq.valid := otherUnit.memReadRequest.valid && simpleAccessPorts.ar.ready
+  simpleSourceQueue.io.enq.bits := otherUnit.memReadRequest.bits.source
   simpleSourceQueue.io.deq.ready := simpleAccessPorts.r.fire
 
   val simpleDataQueue: Queue[SimpleMemWrite] = Module(new Queue(chiselTypeOf(otherUnit.memWriteRequest.bits), 2))