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timing debug #908

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qinjun-li
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  • [rtl] merge csrInterface to laneRequest.
  • [rtl] connect laneRequest with shifter.
  • [rtl] connect vrf read with shifter.
  • [rtl] Pipe result in float adder.
  • [rtl] connect vrf write with shifter.
  • [rtl] add mask control.
  • [rtl] duplicate v0 in lsu.
  • [om] bug fix on the ReferenceTarget pattern match
  • [om] retime FloatAdder in Permutation
  • [rtl] fix mask update in lane.
  • [code] format.
  • [rtl] fix vrf read result.
  • [rtl] Check whether the order of instruction index is clear in the sequencer.
  • [rtl] Pipe result in MaskCompress.
  • [rtl] Add read token in store unit.
  • [rtl] retime compress unit.
  • [rtl] retime compress unit.
  • [rtl] cut pipe in compress unit.
  • [rtl] pipe instructionFinished in sequencer.

@qinjun-li qinjun-li force-pushed the timing-debug branch 9 times, most recently from a55c853 to b1245cc Compare December 26, 2024 08:30
@Avimitin Avimitin added the PD-Lane Ask T1-Inhouse Flow to Run Physical Design for Lane label Dec 27, 2024
@qinjun-li qinjun-li removed the PD-Lane Ask T1-Inhouse Flow to Run Physical Design for Lane label Dec 27, 2024
@qinjun-li qinjun-li force-pushed the timing-debug branch 2 times, most recently from 0451da1 to 9ea63f2 Compare December 30, 2024 08:00
@Avimitin Avimitin force-pushed the timing-debug branch 2 times, most recently from 1bdd4ab to 209fb8f Compare December 30, 2024 10:44
@qinjun-li qinjun-li force-pushed the timing-debug branch 2 times, most recently from 5c77700 to cf0eaf1 Compare December 30, 2024 13:04
sequencer and others added 9 commits December 31, 2024 14:21
@sequencer @qinjun-li
[om] bug fix on the ReferenceTarget pattern match
e6899f0
@sequencer @qinjun-li
[om] retime FloatAdder in Permutation
d4b6cd4
@qinjun-li
[code] format.
a064281
@qinjun-li
[rtl] Modify the timing related bundle.
caf96c9
@qinjun-li
[rtl] retiming float add in mask reduce.
3e6658b
@qinjun-li
[rtl] Modifications related to timing in lane:
c249c9d 
1. merge csrInterface to laneRequest.
2. add mask control in lane, request mask by shifter.
3. add vrf release in lane, delete order check & slot free check.
@qinjun-li
[rtl] Fix connection related timing issues:
98c517b 
1. Use shifter for long distance connections.
2. Make a copy of v0 in lsu.
3. Reorder the read results in the mask unit.
   Because the time when the reading results come back cannot be determined in advance
@qinjun-li
[rtl] Processing units waiting for read results.
df7bb43
@qinjun-li
[rtl] Manual retiming compress unit.
51f7ea8
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3 participants
@qinjun-li @Avimitin @sequencer