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honor the 'ready' signal from the GCD output #153
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wunderabt
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freechipsproject:master
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wunderabt:decoupledgcd-with-backpressure
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Original file line number | Diff line number | Diff line change |
---|---|---|
|
@@ -420,26 +420,26 @@ | |
" val x = Reg(UInt())\n", | ||
" val y = Reg(UInt())\n", | ||
" val busy = RegInit(false.B)\n", | ||
" val resultValid = RegInit(false.B)\n", | ||
"\n", | ||
" input.ready := ! busy\n", | ||
" output.valid := resultValid\n", | ||
" output.bits := DontCare\n", | ||
" output.valid := false.B\n", | ||
"\n", | ||
" when(busy) {\n", | ||
" // during computation keep subtracting the smaller from the larger\n", | ||
" when(x > y) {\n", | ||
" x := x - y\n", | ||
" when(y > 0.U) {\n", | ||
" when(x > y) {\n", | ||
" x := x - y\n", | ||
" }.otherwise {\n", | ||
" y := y - x\n", | ||
" }\n", | ||
" }.otherwise {\n", | ||
" y := y - x\n", | ||
" }\n", | ||
" when(y === 0.U) {\n", | ||
" // when y becomes zero computation is over, signal valid data to output\n", | ||
" output.bits.value1 := xInitial\n", | ||
" output.bits.value2 := yInitial\n", | ||
" output.bits.gcd := x\n", | ||
" output.valid := true.B\n", | ||
" busy := false.B\n", | ||
" busy := ! output.ready\n", | ||
" }\n", | ||
" }.otherwise {\n", | ||
" when(input.valid) {\n", | ||
|
@@ -450,7 +450,7 @@ | |
" xInitial := bundle.value1\n", | ||
" yInitial := bundle.value2\n", | ||
" busy := true.B\n", | ||
" resultValid := false.B\n", | ||
" output.valid := false.B\n", | ||
" }\n", | ||
" }\n", | ||
"}\n" | ||
|
@@ -503,6 +503,36 @@ | |
"}\n" | ||
] | ||
}, | ||
{ | ||
"cell_type": "code", | ||
"execution_count": null, | ||
"metadata": {}, | ||
"outputs": [], | ||
"source": [ | ||
"// test for backpressure\n", | ||
"test(new DecoupledGcd(16)) { dut =>\n", | ||
" dut.input.initSource().setSourceClock(dut.clock)\n", | ||
" dut.output.initSink().setSinkClock(dut.clock)\n", | ||
"\n", | ||
" val testValues = for { x <- 1 to 10; y <- 1 to 10} yield (x, y)\n", | ||
" val inputSeq = testValues.map { case (x, y) =>\n", | ||
" (new GcdInputBundle(16)).Lit(_.value1 -> x.U, _.value2 -> y.U)\n", | ||
" }\n", | ||
" val resultSeq = testValues.map { case (x, y) =>\n", | ||
" new GcdOutputBundle(16).Lit(_.value1 -> x.U, _.value2 -> y.U, _.gcd -> BigInt(x).gcd(BigInt(y)).U)\n", | ||
" }\n", | ||
"\n", | ||
" for((inputVal, resultVal) <- inputSeq zip resultSeq) {\n", | ||
" dut.input.enqueueNow(inputVal)\n", | ||
" dut.output.ready.poke(false.B)\n", | ||
" for(_ <- 0 to 10) {\n", | ||
" dut.clock.step(1)\n", | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. this is my poor mans solution for the clock divider - set the ouput in a non-ready state and idle for come cycles. |
||
" }\n", | ||
" dut.output.expectDequeueNow(resultVal)\n", | ||
" }\n", | ||
"}" | ||
] | ||
}, | ||
{ | ||
"cell_type": "markdown", | ||
"metadata": {}, | ||
|
@@ -531,4 +561,4 @@ | |
}, | ||
"nbformat": 4, | ||
"nbformat_minor": 2 | ||
} | ||
} |
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What I want to do is to use slower clock for the sink so that there is greater chance that a
fork
+join
approach runs into a backpressure scenario but I don't know how to write a ClockDivider here? @edwardcwang or @ducky64 do you maybe have some directions?