riscv: virt: Relax the configurations related to hart/thread number

Do not force the CFG_TEE_CORE_NB_CORE and CFG_NUM_THREADS to be 1, since we may run SMP system which has multiple harts and threads. Signed-off-by: Alvin Chang <[email protected]> Acked-by: Jerome Forissier <[email protected]> Reviewed-by: Marouene Boubakri <[email protected]>
gagachang · Dec 7, 2023 · c6a4b1c · c6a4b1c
1 parent 6004e80
commit c6a4b1c
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/core/arch/riscv/plat-virt/conf.mk b/core/arch/riscv/plat-virt/conf.mk
@@ -13,8 +13,8 @@ $(call force,CFG_WITH_STACK_CANARIES,n)
 $(call force,CFG_CORE_SANITIZE_KADDRESS,n)
 
 # Hart-related flags
-$(call force,CFG_TEE_CORE_NB_CORE,1)
-$(call force,CFG_NUM_THREADS,1)
+CFG_TEE_CORE_NB_CORE ?= 1
+CFG_NUM_THREADS ?= 1
 $(call force,CFG_BOOT_SYNC_CPU,y)
 
 # RISC-V-specific flags