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modules/zstd: Add verilog generation and benchmarking rules for Seque…
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…nceExecutor

Internal-tag: [#54705]
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@rw1nkler
rw1nkler committed Feb 14, 2024
1 parent bd07cc1 commit a0bffc4
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84 changes: 84 additions & 0 deletions xls/modules/zstd/BUILD
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Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,7 @@ load("@rules_hdl//verilog:providers.bzl", "verilog_library")
load(
"//xls/build_rules:xls_build_defs.bzl",
"xls_benchmark_ir",
"xls_benchmark_verilog",
"xls_dslx_library",
"xls_dslx_test",
"xls_dslx_verilog",
Expand Down Expand Up @@ -618,3 +619,86 @@ xls_dslx_test(
},
library = ":sequence_executor_dslx",
)

xls_dslx_verilog(
name = "sequence_executor_verilog",
codegen_args = {
"module_name": "sequence_executor",
"generator": "pipeline",
"delay_model": "asap7",
"ram_configurations": ",".join([
"{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format(
latency = 5,
ram_name = "ram{}".format(num),
rd_req = "sequence_executor__rd_req_m{}_s".format(num),
rd_resp = "sequence_executor__rd_resp_m{}_r".format(num),
wr_req = "sequence_executor__wr_req_m{}_r".format(num),
wr_resp = "sequence_executor__wr_resp_m{}_r".format(num),
)
for num in range(7)
]),
"pipeline_stages": "8",
"reset": "rst",
"reset_data_path": "true",
"reset_active_low": "false",
"reset_asynchronous": "true",
"flop_inputs": "false",
"flop_single_value_channels": "false",
"flop_outputs": "false",
"worst_case_throughput": "1",
"use_system_verilog": "false",
},
dslx_top = "SequenceExecutorZstd",
library = ":sequence_executor_dslx",
opt_ir_args = {
"inline_procs": "true",
"top": "__sequence_executor__SequenceExecutorZstd__SequenceExecutor_0__64_0_0_0_13_8192_65536_next",
},
verilog_file = "sequence_executor.v",
)

xls_benchmark_ir(
name = "sequence_executor_ir_benchmark",
src = ":sequence_executor_verilog.opt.ir",
benchmark_ir_args = {
"pipeline_stages": "8",
"delay_model": "asap7",
},
)

xls_benchmark_verilog(
name = "sequence_executor_verilog_benchmark",
verilog_target = "sequence_executor_verilog",
)

verilog_library(
name = "sequence_executor_lib",
srcs = [
":sequence_executor.v",
],
)

synthesize_rtl(
name = "sequence_executor_asap7",
standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt",
top_module = "sequence_executor",
deps = [
":sequence_executor_lib",
],
)

benchmark_synth(
name = "sequence_executor_benchmark_synth",
synth_target = ":sequence_executor_asap7",
)

place_and_route(
name = "sequence_executor_place_and_route",
clock_period = "750",
core_padding_microns = 2,
min_pin_distance = "0.5",
placement_density = "0.30",
skip_detailed_routing = True,
synthesized_rtl = ":sequence_executor_asap7",
target_die_utilization_percentage = "10",
)
1 change: 1 addition & 0 deletions xls/modules/zstd/common.x
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Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,7 @@ pub const MAX_ID = u32::MAX;
pub const SYMBOL_WIDTH = u32:8;
pub const BLOCK_SIZE_WIDTH = u32:21;
pub const OFFSET_WIDTH = u32:22;
pub const HISTORY_BUFFER_SIZE_KB = u32:64;

pub type BlockData = bits[DATA_WIDTH];
pub type BlockPacketLength = u32;
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60 changes: 60 additions & 0 deletions xls/modules/zstd/sequence_executor.x
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Original file line number Diff line number Diff line change
Expand Up @@ -1133,6 +1133,66 @@ proc SequenceExecutor<HISTORY_BUFFER_SIZE_KB: u32,
}
}

const ZSTD_HISTORY_BUFFER_SIZE_KB: u32 = u32:64;
const ZSTD_RAM_SIZE = ram_size(ZSTD_HISTORY_BUFFER_SIZE_KB);
const ZSTD_RAM_ADDR_WIDTH = ram_addr_width(ZSTD_HISTORY_BUFFER_SIZE_KB);

pub proc SequenceExecutorZstd {

init { }

config(
input_r: chan<SequenceExecutorPacket> in,
output_s: chan<ZstdDecodedPacket> out,
rd_req_m0_s: chan<ram::ReadReq<ZSTD_RAM_ADDR_WIDTH, RAM_NUM_PARTITIONS>> out,
rd_req_m1_s: chan<ram::ReadReq<ZSTD_RAM_ADDR_WIDTH, RAM_NUM_PARTITIONS>> out,
rd_req_m2_s: chan<ram::ReadReq<ZSTD_RAM_ADDR_WIDTH, RAM_NUM_PARTITIONS>> out,
rd_req_m3_s: chan<ram::ReadReq<ZSTD_RAM_ADDR_WIDTH, RAM_NUM_PARTITIONS>> out,
rd_req_m4_s: chan<ram::ReadReq<ZSTD_RAM_ADDR_WIDTH, RAM_NUM_PARTITIONS>> out,
rd_req_m5_s: chan<ram::ReadReq<ZSTD_RAM_ADDR_WIDTH, RAM_NUM_PARTITIONS>> out,
rd_req_m6_s: chan<ram::ReadReq<ZSTD_RAM_ADDR_WIDTH, RAM_NUM_PARTITIONS>> out,
rd_req_m7_s: chan<ram::ReadReq<ZSTD_RAM_ADDR_WIDTH, RAM_NUM_PARTITIONS>> out,
rd_resp_m0_r: chan<ram::ReadResp<RAM_DATA_WIDTH>> in,
rd_resp_m1_r: chan<ram::ReadResp<RAM_DATA_WIDTH>> in,
rd_resp_m2_r: chan<ram::ReadResp<RAM_DATA_WIDTH>> in,
rd_resp_m3_r: chan<ram::ReadResp<RAM_DATA_WIDTH>> in,
rd_resp_m4_r: chan<ram::ReadResp<RAM_DATA_WIDTH>> in,
rd_resp_m5_r: chan<ram::ReadResp<RAM_DATA_WIDTH>> in,
rd_resp_m6_r: chan<ram::ReadResp<RAM_DATA_WIDTH>> in,
rd_resp_m7_r: chan<ram::ReadResp<RAM_DATA_WIDTH>> in,
wr_req_m0_s: chan<ram::WriteReq<ZSTD_RAM_ADDR_WIDTH, RAM_DATA_WIDTH, RAM_NUM_PARTITIONS>> out,
wr_req_m1_s: chan<ram::WriteReq<ZSTD_RAM_ADDR_WIDTH, RAM_DATA_WIDTH, RAM_NUM_PARTITIONS>> out,
wr_req_m2_s: chan<ram::WriteReq<ZSTD_RAM_ADDR_WIDTH, RAM_DATA_WIDTH, RAM_NUM_PARTITIONS>> out,
wr_req_m3_s: chan<ram::WriteReq<ZSTD_RAM_ADDR_WIDTH, RAM_DATA_WIDTH, RAM_NUM_PARTITIONS>> out,
wr_req_m4_s: chan<ram::WriteReq<ZSTD_RAM_ADDR_WIDTH, RAM_DATA_WIDTH, RAM_NUM_PARTITIONS>> out,
wr_req_m5_s: chan<ram::WriteReq<ZSTD_RAM_ADDR_WIDTH, RAM_DATA_WIDTH, RAM_NUM_PARTITIONS>> out,
wr_req_m6_s: chan<ram::WriteReq<ZSTD_RAM_ADDR_WIDTH, RAM_DATA_WIDTH, RAM_NUM_PARTITIONS>> out,
wr_req_m7_s: chan<ram::WriteReq<ZSTD_RAM_ADDR_WIDTH, RAM_DATA_WIDTH, RAM_NUM_PARTITIONS>> out,
wr_resp_m0_r: chan<ram::WriteResp> in,
wr_resp_m1_r: chan<ram::WriteResp> in,
wr_resp_m2_r: chan<ram::WriteResp> in,
wr_resp_m3_r: chan<ram::WriteResp> in,
wr_resp_m4_r: chan<ram::WriteResp> in,
wr_resp_m5_r: chan<ram::WriteResp> in,
wr_resp_m6_r: chan<ram::WriteResp> in,
wr_resp_m7_r: chan<ram::WriteResp> in
) {
spawn SequenceExecutor<ZSTD_HISTORY_BUFFER_SIZE_KB> (
input_r, output_s,
rd_req_m0_s, rd_req_m1_s, rd_req_m2_s, rd_req_m3_s,
rd_req_m4_s, rd_req_m5_s, rd_req_m6_s, rd_req_m7_s,
rd_resp_m0_r, rd_resp_m1_r, rd_resp_m2_r, rd_resp_m3_r,
rd_resp_m4_r, rd_resp_m5_r, rd_resp_m6_r, rd_resp_m7_r,
wr_req_m0_s, wr_req_m1_s, wr_req_m2_s, wr_req_m3_s,
wr_req_m4_s, wr_req_m5_s, wr_req_m6_s, wr_req_m7_s,
wr_resp_m0_r, wr_resp_m1_r, wr_resp_m2_r, wr_resp_m3_r,
wr_resp_m4_r, wr_resp_m5_r, wr_resp_m6_r, wr_resp_m7_r
);
}

next (tok: token, state: ()) { }
}

const LITERAL_TEST_INPUT_DATA = SequenceExecutorPacket[6]:[
SequenceExecutorPacket {
msg_type: SequenceExecutorMessageType::LITERAL,
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