Skip to content

Issues: google/xls

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort

Issues list

[enhancement] Rethink Channel Legalization codegen Related to emitting (System)Verilog. enhancement New feature or request
#1647 opened Oct 4, 2024 by grebe
[enhancement] DSLX Polymorphism dslx DSLX (domain specific language) implementation / front-end enhancement New feature or request
#1646 opened Oct 4, 2024 by grebe
[enhancement] Put module_builder's functions in a shared package codegen Related to emitting (System)Verilog. enhancement New feature or request
#1643 opened Oct 3, 2024 by grebe
[enhancement] Name legalization should choose keywords based on configuration codegen Related to emitting (System)Verilog. enhancement New feature or request
#1641 opened Oct 2, 2024 by grebe
[enhancement] Make an easy path to add DSLX models to a DUT enhancement New feature or request
#1638 opened Sep 27, 2024 by grebe
Extern types don't codegen correctly when array-typed codegen Related to emitting (System)Verilog.
#1637 opened Sep 27, 2024 by grebe
ir_conv: chan array cannot be destructed w/ wildcards dslx DSLX (domain specific language) implementation / front-end ir 🧦 sox
#1632 opened Sep 25, 2024 by proppy
ir_conv: chan array cannot be created from from existing chans dslx DSLX (domain specific language) implementation / front-end ir 🧦 sox
#1631 opened Sep 25, 2024 by proppy
Refactor channel->port mapping in signature codegen Related to emitting (System)Verilog. stitching Issues related to stitching, multi-proc codegen, and integration with external verilog modules
#1628 opened Sep 24, 2024 by grebe
[enhancement] XLS playground colab should be documented in our markdown docs documentation Improvements or additions to documentation enhancement New feature or request
#1626 opened Sep 24, 2024 by cdleary
FUZZER: eval_proc_main crash 0330 bug Something isn't working or is incorrect fuzz jit
#1624 opened Sep 23, 2024 by allight
Document array_concat IR operation documentation Improvements or additions to documentation ir
#1619 opened Sep 20, 2024 by ericastor
jit crash, 2024-09-20_67c5 bug Something isn't working or is incorrect fuzz jit
#1618 opened Sep 20, 2024 by hzeller
Hoist operations above selects if it enables constant folding optimizer Related to IR optimization or analysis
#1611 opened Sep 18, 2024 by meheff
cpp_transpiler should emit DSLX constants enhancement New feature or request 🧦 sox
#1610 opened Sep 17, 2024 by mikex-oss
Drop Node::SetId() ir
#1601 opened Sep 11, 2024 by grebe
Token arrays needed to supplement channel arrays dslx DSLX (domain specific language) implementation / front-end enhancement New feature or request
#1600 opened Sep 11, 2024 by mikex-oss DSLX Next
Expand or Move away fromParametricExpression dslx DSLX (domain specific language) implementation / front-end
#1597 opened Sep 11, 2024 by erinzmoore DSLX large projects
ProTip! Type g i on any issue or pull request to go back to the issue listing page.