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[FIRRTL] Add View Intrinsic #8026

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[FIRRTL] Add View Intrinsic #8026

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12 changes: 12 additions & 0 deletions include/circt/Dialect/FIRRTL/FIRRTLIntrinsics.td
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Original file line number Diff line number Diff line change
Expand Up @@ -231,4 +231,16 @@ def DPICallIntrinsicOp : FIRRTLOp<"int.dpi.call",
let hasVerifier = 1;
}

def ViewIntrinsicOp : FIRRTLOp<"view", []> {
let summary = "A SystemVerilog Interface only usable for waveform debugging";
let description = [{
This will become a SystemVerilog Interface that is driven by its arguments.
This is _not_ intended to be used for anything other than assistance when
debugging in a waveform. This is _not_ a true SystemVerilog Interface, it
is only lowered to one.
}];
let arguments = (ins StrAttr:$name, AugmentedBundleType:$augmentedType, Variadic<RefType>:$probes);
let assemblyFormat = "$name `,` $augmentedType (`,` $probes^)? attr-dict `:` type($probes)";
}

#endif // CIRCT_DIALECT_FIRRTL_FIRRTLINTRINSICS_TD
33 changes: 33 additions & 0 deletions test/Dialect/FIRRTL/round-trip.mlir
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Expand Up @@ -40,6 +40,39 @@ firrtl.module @Intrinsics(in %ui : !firrtl.uint, in %clock: !firrtl.clock, in %u
%p = firrtl.int.generic "params" <FORMAT: none = "foobar"> : () -> !firrtl.bundle<x: uint<1>>
%po = firrtl.int.generic "params_and_operand" <X: i64 = 123> %ui1 : (!firrtl.uint<1>) -> !firrtl.clock
firrtl.int.generic "inputs" %clock, %ui1, %clock : (!firrtl.clock, !firrtl.uint<1>, !firrtl.clock) -> ()

%probe = firrtl.wire : !firrtl.probe<uint<1>>
// CHECK: firrtl.view "View"
// CHECK-SAME: <{
// CHECK-SAME: elements = [
// CHECK-SAME: {
// CHECK-SAME: class = "sifive.enterprise.grandcentral.AugmentedGroundType",
// CHECK-SAME: id = 0 : i64,
// CHECK-SAME: name = "baz"
// CHECK-SAME: },
// CHECK-SAME: {
// CHECK-SAME: class = "sifive.enterprise.grandcentral.AugmentedGroundType",
// CHECK-SAME: id = 0 : i64,
// CHECK-SAME: name = "qux"
// CHECK-SAME: }
// CHECK-SAME: ]
// CHECK-SAME: }>, %probe, %probe : !firrtl.probe<uint<1>>, !firrtl.probe<uint<1>>
firrtl.view "View", <{
class = "sifive.enterprise.grandcentral.AugmentedBundleType",
defName = "Bar",
elements = [
{
class = "sifive.enterprise.grandcentral.AugmentedGroundType",
id = 0 : i64,
name = "baz"
},
{
class = "sifive.enterprise.grandcentral.AugmentedGroundType",
id = 0 : i64,
name = "qux"
}
]
}>, %probe, %probe : !firrtl.probe<uint<1>>, !firrtl.probe<uint<1>>
}

// CHECK-LABEL: firrtl.module @FPGAProbe
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