(DNM) Comment out RaiseSpecialOps

nod-ai · Nov 16, 2023 · c36d506 · c36d506
1 parent 326100b
commit c36d506
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Showing 4 changed files with 9 additions and 21 deletions.
diff --git a/compiler/src/iree/compiler/Codegen/LLVMCPU/LLVMCPULowerExecutableTarget.cpp b/compiler/src/iree/compiler/Codegen/LLVMCPU/LLVMCPULowerExecutableTarget.cpp
@@ -237,9 +237,8 @@ void LLVMCPULowerExecutableTargetPass::runOnOperation() {
 
     case IREE::Codegen::DispatchLoweringPassPipeline::AccelMatmulExpert: {
       TilingConfig tilingConfig = getTilingConfigForPipeline(moduleOp);
-      addAccelMatmulExpertPassPipeline(executableLoweringPipeline,
-                                       tilingConfig,
-                                       enableAccelMicrokernels);
+      addAccelMatmulExpertPassPipeline(pipeline,
+                                       tilingConfig);
       break;
     }
   }
@@ -248,6 +247,7 @@ void LLVMCPULowerExecutableTargetPass::runOnOperation() {
     return signalPassFailure();
   }
 }
+}
 
 std::unique_ptr<OperationPass<IREE::HAL::ExecutableVariantOp>>
 createLLVMCPULowerExecutableTargetPass() {

diff --git a/compiler/src/iree/compiler/Codegen/LLVMCPU/Passes.cpp b/compiler/src/iree/compiler/Codegen/LLVMCPU/Passes.cpp
@@ -568,29 +568,18 @@ void addMmt4dTilingExpertPassPipeline(OpPassManager &passManager,
 }
 
 void addAccelMatmulExpertPassPipeline(OpPassManager &passManager,
-                                      TilingConfig &tilingConfig,
-                                      bool enableAccelMicrokernels) {
+                                      TilingConfig &tilingConfig) {
   addTileAndDistributePasses(passManager);
 
   OpPassManager &nestedModulePM = passManager.nest<ModuleOp>();
 
-  if (enableAccelMicrokernels) {
-    nestedModulePM.addPass(createLLVMCPULowerToAccelUKernelsPass());
-  } else {
-    nestedModulePM.addNestedPass<func::FuncOp>(createLLVMCPUTileAndFusePass(
-        static_cast<int64_t>(tilingConfig.getVectorCommonParallelLevel())));
-    nestedModulePM.addNestedPass<func::FuncOp>(createLLVMCPUTilePass(
-        static_cast<int64_t>(tilingConfig.getVectorReductionLevel())));
-    nestedModulePM.addNestedPass<func::FuncOp>(
-        createGenericVectorizationPass());
-    nestedModulePM.addNestedPass<func::FuncOp>(
-        createHoistRedundantVectorTransfersPass());
-  }
+
+  nestedModulePM.addPass(createLLVMCPULowerToAccelUKernelsPass());
 
   nestedModulePM.addNestedPass<func::FuncOp>(createCanonicalizerPass());
   nestedModulePM.addNestedPass<func::FuncOp>(createCSEPass());
 
-  addBufferizePasses(nestedModulePM);
+  addCPUBufferizePasses(nestedModulePM);
 }
 
 void addCPUDataTilingPipeline(OpPassManager &passManager,

diff --git a/compiler/src/iree/compiler/Codegen/LLVMCPU/Passes.h b/compiler/src/iree/compiler/Codegen/LLVMCPU/Passes.h
@@ -175,8 +175,7 @@ void addMmt4dTilingExpertPassPipeline(OpPassManager &passManager,
                                       bool enableMicrokernels);
 
 void addAccelMatmulExpertPassPipeline(OpPassManager &passManager,
-                                      TilingConfig &tilingConfig,
-                                      bool enableAccelMicrokernels);
+                                      TilingConfig &tilingConfig);
 
 void addMultiTilingExpertPassPipeline(
     OpPassManager &passManager, TilingConfig &tilingConfig, bool enablePeeling,

diff --git a/compiler/src/iree/compiler/GlobalOptimization/Passes.cpp b/compiler/src/iree/compiler/GlobalOptimization/Passes.cpp
@@ -73,7 +73,7 @@ void buildGlobalOptimizationPassPipeline(
       // RaiseSpecialOps, by virtue of implementing various peephole
       // optimizations, is sensitive to surrounding IR structure. Thus we run
       // this pass both before unit dim folding + consteval, as well as after.
-      .addPass(IREE::Flow::createRaiseSpecialOps)
+      // .addPass(IREE::Flow::createRaiseSpecialOps)
       .addPass(IREE::Flow::createFoldUnitExtentDimsPass)
       .addPass([&]() {
         return createFuseDequantizationMatmulPass(