Workshop 2

Go to Guide.md

Implement simple (logical) combinational functions, along with a testbench
Implement an ALU that computes those functions
Implement a simple control FSM which takes in an instruction register and runs a decode and execute stage on any of the possible instruction opcodes

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
.gitignore		.gitignore
Guide.md		Guide.md
Instructions.md		Instructions.md
README.md		README.md
alu.v		alu.v
alu_tb.v		alu_tb.v
and.v		and.v
and_tb.v		and_tb.v
cpu.v		cpu.v
full_adder.v		full_adder.v
full_adder_tb.v		full_adder_tb.v
instructions.v		instructions.v
not.v		not.v
not_tb.v		not_tb.v
or.v		or.v
or_tb.v		or_tb.v
sequential.v		sequential.v
sequential_tb.v		sequential_tb.v
xor.v		xor.v
xor_tb.v		xor_tb.v

Provide feedback