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Latest (v0.0-3373-g54e37ed0) verison of Verible (#319)
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* Latest (v0.0-3373-g54e37ed0) verison of Verible

* Update verible version

* Verible cleanup

* Verible cleanup
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@MikeOpenHWGroup
MikeOpenHWGroup authored Aug 30, 2023
1 parent 22e08ba commit 12bc79e
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18 changes: 9 additions & 9 deletions .github/workflows/lint.yml
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@@ -1,4 +1,4 @@
# Copyright 2021 OpenHW Group
# Copyright 2021, 2023 OpenHW Group
# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1

Expand All @@ -7,7 +7,7 @@ name: lint
on: [push, pull_request]

env:
VERIBLE_VERSION: 0.0-1051-gd4cd328
VERIBLE_VERSION: 0.0-3410-g398a8505

jobs:
##################
Expand All @@ -18,8 +18,8 @@ jobs:
# This job runs on Linux (fixed ubuntu version)
runs-on: ubuntu-20.04
steps:
- uses: actions/checkout@v2
- uses: actions/setup-python@v2
- uses: actions/checkout@v3
- uses: actions/setup-python@v3
with:
python-version: 3.9
- name: Install requirements
Expand All @@ -29,7 +29,7 @@ jobs:
set -e
mkdir -p build/verible
cd build/verible
curl -Ls -o verible.tar.gz https://github.com/google/verible/releases/download/v$VERIBLE_VERSION/verible-v$VERIBLE_VERSION-Ubuntu-18.04-bionic-x86_64.tar.gz
curl -Ls -o verible.tar.gz https://github.com/google/verible/releases/download/v$VERIBLE_VERSION/verible-v$VERIBLE_VERSION-Ubuntu-20.04-focal-x86_64.tar.gz
sudo mkdir -p /tools/verible && sudo chmod 777 /tools/verible
tar -C /tools/verible -xf verible.tar.gz --strip-components=1
echo "PATH=$PATH:/tools/verible/bin" >> $GITHUB_ENV
Expand All @@ -46,8 +46,8 @@ jobs:
name: Vendor Up-to-Date
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- uses: actions/setup-python@v2
- uses: actions/checkout@v3
- uses: actions/setup-python@v3
with:
python-version: 3.9
- name: Install requirements
Expand Down Expand Up @@ -88,8 +88,8 @@ jobs:
# name: YAML Sources
# runs-on: ubuntu-latest
# steps:
# - uses: actions/checkout@v2
# - uses: actions/setup-python@v2
# - uses: actions/checkout@v3
# - uses: actions/setup-python@v3
# with:
# python-version: 3.9
# - name: Install requirements
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4 changes: 2 additions & 2 deletions README.md
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Expand Up @@ -157,7 +157,7 @@ If your changes introduce any more Verilator lint warnings, you either need to f

### Verible format check

Standard formating is enforced by [Verible](https://github.com/google/verible). The command used is
Standard formating is enforced by [Verible](https://github.com/chipsalliance/verible). The command used is
```
util/format-verible
```
Expand All @@ -167,7 +167,7 @@ Two important things to note.

1. If you do not have Verible installed (which is likely), then `util/format-verible` will silently do nothing.

2. You must install the correct version of Verible, currently v0.0-1051-gd4cd328. GitHub has [prebuilt versions](https://github.com/google/verible/releases/tag/v0.0-1051-gd4cd328). The version may change in the future. In the event of the check failing, the details with the failure will tell you which version was used.
2. You must install the correct version of Verible, currently v0.0-3410-g398a8505. Chips Alliance has [prebuilt versions](https://github.com/chipsalliance/verible/releases?ref=circuitcove.com). The version may change in the future. In the event of the check failing, the details with the failure will tell you which version was used.

## References

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3 changes: 1 addition & 2 deletions rtl/core-v-mcu/components/apb_soc_ctrl.sv
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Expand Up @@ -111,8 +111,7 @@ module apb_soc_ctrl #(


);
localparam IDX_WIDTH =
`LOG2(`N_IO);
localparam IDX_WIDTH = `LOG2(`N_IO);
localparam CONFIG = 12'h4??;

logic [ IDX_WIDTH-1:0] r_io_pad;
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4 changes: 1 addition & 3 deletions rtl/core-v-mcu/soc/interleaved_crossbar.sv
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Expand Up @@ -44,9 +44,7 @@ module interleaved_crossbar #(
//Elaboration time asserations
//Number of slaves must be power of two
if ((NR_SLAVE_PORTS & (NR_SLAVE_PORTS - 1)) != 0) begin
$error(
"NR_SLAVE_PORTS must be power of two but was %d", NR_SLAVE_PORTS
);
$error("NR_SLAVE_PORTS must be power of two but was %d", NR_SLAVE_PORTS);
end

// Explode the input interface array to arrays of individual signals
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67 changes: 34 additions & 33 deletions rtl/core-v-mcu/top/soc_domain.sv
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Expand Up @@ -156,7 +156,7 @@ module soc_domain
dataaddr: dm::DataAddr
};

dm::hartinfo_t [ NrHarts-1:0 ] hartinfo;
dm::hartinfo_t [ NrHarts-1:0] hartinfo;

/*
This module has been tested only with the default parameters.
Expand All @@ -166,49 +166,49 @@ module soc_domain
//***************** SIGNALS DECLARATION ******************
//********************************************************

logic s_dmactive;
logic s_dmactive;

logic s_stoptimer;
logic s_wd_expired;
logic [ 1:0] s_fc_hwpe_events;
logic [ 31:0] s_fc_events;
logic s_stoptimer;
logic s_wd_expired;
logic [ 1:0] s_fc_hwpe_events;
logic [ 31:0] s_fc_events;

logic [ 7:0] s_soc_events_ack;
logic [ 7:0] s_soc_events_val;
logic [ 7:0] s_soc_events_ack;
logic [ 7:0] s_soc_events_val;

logic s_timer_lo_event;
logic s_timer_hi_event;
logic s_timer_lo_event;
logic s_timer_hi_event;

logic [EVNT_WIDTH-1:0] s_cl_event_data;
logic s_cl_event_valid;
logic s_cl_event_ready;
logic [EVNT_WIDTH-1:0] s_cl_event_data;
logic s_cl_event_valid;
logic s_cl_event_ready;


logic [ 7:0] [31:0] s_apb_mpu_rules;
logic s_supervisor_mode;
logic [ 7:0][31:0] s_apb_mpu_rules;
logic s_supervisor_mode;

logic [ 31:0] s_fc_bootaddr;
logic [ 31:0] s_fc_bootaddr;

logic s_periph_clk;
logic s_periph_rst;
logic s_soc_clk;
logic s_soc_rstn;
logic s_rstn_glob;
logic s_sel_fll_clk;
logic s_periph_clk;
logic s_periph_rst;
logic s_soc_clk;
logic s_soc_rstn;
logic s_rstn_glob;
logic s_sel_fll_clk;

logic s_dma_pe_evt;
logic s_dma_pe_irq;
logic s_pf_evt;
logic s_dma_pe_evt;
logic s_dma_pe_irq;
logic s_pf_evt;

logic s_fc_fetchen;
logic [ NrHarts-1:0] dm_debug_req;
logic s_fc_fetchen;
logic [ NrHarts-1:0] dm_debug_req;

logic jtag_req_valid;
logic debug_req_ready;
logic jtag_resp_ready;
logic jtag_resp_valid;
dm::dmi_req_t jtag_dmi_req;
dm::dmi_resp_t debug_resp;
logic jtag_req_valid;
logic debug_req_ready;
logic jtag_resp_ready;
logic jtag_resp_valid;
dm::dmi_req_t jtag_dmi_req;
dm::dmi_resp_t debug_resp;
logic slave_grant, slave_valid, dm_slave_req, dm_slave_we;
logic [31:0] dm_slave_addr, dm_slave_wdata, dm_slave_rdata;
logic [ 3:0] dm_slave_be;
Expand Down Expand Up @@ -395,6 +395,7 @@ module soc_domain

.supervisor_mode_o(s_supervisor_mode)
);

assign s_soc_rstn = !(!rstn_glob_i | s_wd_expired | s_periph_rst);

soc_interconnect_wrap #(
Expand Down
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