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Merge pull request #2228 from XavierAubert/cv32e40p/dev_dd_W40a
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TB & corev-dv stream generations fixes
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@MikeOpenHWGroup
MikeOpenHWGroup authored Oct 19, 2023
2 parents 9ad9083 + 02ee752 commit 274b984
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Showing 27 changed files with 1,364 additions and 541 deletions.
15 changes: 10 additions & 5 deletions bin/cv_regress
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Original file line number Diff line number Diff line change
Expand Up @@ -137,11 +137,6 @@ def read_file(args, file):
for k in testlist['tests']:
t = testlist['tests'][k]

try:
if args.simulator in t['skip_sim']:
continue
except KeyError:
pass
test = cv_regression.Test(name=k, simulator=args.simulator, **t)
if args.cov:
test.set_cov()
Expand Down Expand Up @@ -173,6 +168,16 @@ def read_file(args, file):
elif test.num != 1:
test.num = int(args.num or test.num)

try:
if test.simulator in t['skip_sim']:
logger.info('Skipping test {} due to selected simulator {}'.format(test.name, test.simulator))
continue
if test.cfg in t['skip_sim']:
logger.info('Skipping test {} due to selected cfg {}'.format(test.name, test.cfg))
continue
except KeyError:
pass

regression.add_test(test)

return regression
Expand Down
2 changes: 1 addition & 1 deletion bin/templates/regress_rmdb.j2
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Original file line number Diff line number Diff line change
Expand Up @@ -119,7 +119,7 @@
<parameters>
<parameter name="t_cfg" type="tcl">[getParameterByPriority "{{config}}" "{{t.cfg}}" "(%build_config:%)"]</parameter>
<parameter name="t_test_cfg" type="tcl">[getParameterByPriority "" "{{t.test_cfg}}" "(%build_test_cfg:%)"]</parameter>
<parameter name="t_test_cfg_name" type="tcl">[getTestCfgName (%t_test_cfg:%)]</parameter>
<parameter name="t_test_cfg_name" type="tcl">[getTestCfgName "(%t_test_cfg:%)"]</parameter>
<parameter name="t_iss" type="tcl">[getParameterByPriorityYesOrNo "{{iss}}" "{{t.iss}}" "(%build_iss:%)"]</parameter>
<parameter name="t_cov" type="tcl">[getParameterByPriorityYesOrNo "{{coverage}}" "{{t.cov}}" "(%build_cov:%)"]</parameter>
<parameter name="seeds" type="tcl">[GetRandomValues {{t.num}}]</parameter>
Expand Down
32 changes: 19 additions & 13 deletions cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -322,8 +322,10 @@ class cv32e40p_instr extends riscv_instr;
if(category != SYSTEM) begin
case(format)
I_FORMAT: begin // instr rd,rs1,imm more or less
if(category inside {POST_INC_LOAD, EVENT_LOAD})
asm_str_final = $sformatf("%0s %0s, %0s(%0s%0s)", asm_str, rd.name(), get_imm(), rs1.name(), get_post_incr_str());
if(category == POST_INC_LOAD)
asm_str_final = $sformatf("%0s %0s, (%0s), %0s", asm_str, rd.name(), rs1.name(), get_imm());
else if (category == EVENT_LOAD)
asm_str_final = $sformatf("%0s %0s, %0s(%0s)", asm_str, rd.name(), get_imm(), rs1.name());
else if (category == BITMANIP)
asm_str_final = $sformatf("%0s %0s, %0s, %0s", asm_str, rd.name(), rs1.name(), get_imm());
else if (category == HWLOOP) begin
Expand All @@ -337,12 +339,20 @@ class cv32e40p_instr extends riscv_instr;
asm_str_final = $sformatf("%0s %0s, %0s, %0s", asm_str, rd.name(), rs1.name(), get_imm());
end
R_FORMAT: begin
if (category == POST_INC_LOAD)
asm_str_final = $sformatf("%0s %0s, %0s(%0s%0s)", asm_str, rd.name(), rs2.name(), rs1.name(), get_post_incr_str());
if (category == POST_INC_LOAD) begin
if(is_post_incr)
asm_str_final = $sformatf("%0s %0s, (%0s), %0s", asm_str, rd.name(), rs1.name(), rs2.name());
else
asm_str_final = $sformatf("%0s %0s, %0s(%0s)", asm_str, rd.name(), rs2.name(), rs1.name());
end

else if (category == POST_INC_STORE)
else if (category == POST_INC_STORE) begin
// rd is used as offset (rs3 in mnemonic, no use to add another register in the sv class just for this)
asm_str_final = $sformatf("%0s %0s, %0s(%0s%0s)", asm_str, rs2.name(), rd.name(), rs1.name(), get_post_incr_str());
if(is_post_incr)
asm_str_final = $sformatf("%0s %0s, (%0s), %0s", asm_str, rs2.name(), rs1.name(), rd.name());
else
asm_str_final = $sformatf("%0s %0s, %0s(%0s)", asm_str, rs2.name(), rd.name(), rs1.name());
end

else if (category == BITMANIP && instr_name inside {CV_FF1, CV_FL1, CV_CLB, CV_CNT})
asm_str_final = $sformatf("%0s %0s, %0s", asm_str, rd.name(), rs1.name());
Expand All @@ -363,7 +373,7 @@ class cv32e40p_instr extends riscv_instr;
end
S_FORMAT: begin // instr rs1,rs2,imm
if(category == POST_INC_STORE)
asm_str_final = $sformatf("%0s %0s, %0s(%0s!)", asm_str, rs2.name(), get_imm(), rs1.name());
asm_str_final = $sformatf("%0s %0s, (%0s), %0s", asm_str, rs2.name(), rs1.name(), get_imm());
else if (category inside {ALU, MAC} )
asm_str_final = $sformatf("%0s %0s, %0s, %0s, %0s", asm_str, rd.name(), rs1.name(), rs2.name(), get_imm());
else
Expand Down Expand Up @@ -409,7 +419,7 @@ class cv32e40p_instr extends riscv_instr;
CV_EXTRACT, CV_EXTRACTU, CV_INSERT, CV_BCLR,
CV_BSET, CV_BITREV : get_opcode = 7'b1011011;
// General ALU
CV_ABS, CV_SLET, CV_SLETU, CV_MIN, CV_MINU,
CV_ABS, CV_SLE, CV_SLEU, CV_MIN, CV_MINU,
CV_MAX, CV_MAXU, CV_EXTHS, CV_EXTHZ, CV_EXTBS,
CV_EXTBZ, CV_CLIP, CV_CLIPU, CV_CLIPR, CV_CLIPUR,
CV_ADDNR, CV_ADDUNR, CV_ADDRNR, CV_ADDURNR,
Expand Down Expand Up @@ -571,7 +581,7 @@ class cv32e40p_instr extends riscv_instr;
CV_EXTRACT, CV_EXTRACTU, CV_INSERT : get_func3 = 3'b000;
CV_BCLR, CV_BSET, CV_BITREV : get_func3 = 3'b001;
// General ALU
CV_ABS, CV_SLET, CV_SLETU, CV_MIN, CV_MINU,
CV_ABS, CV_SLE, CV_SLEU, CV_MIN, CV_MINU,
CV_MAX, CV_MAXU, CV_EXTHS, CV_EXTHZ, CV_EXTBS,
CV_EXTBZ, CV_CLIP, CV_CLIPU, CV_CLIPR, CV_CLIPUR,
CV_ADDNR, CV_ADDUNR, CV_ADDRNR, CV_ADDURNR,
Expand Down Expand Up @@ -691,10 +701,6 @@ class cv32e40p_instr extends riscv_instr;
super.update_imm_str();
endfunction

virtual function string get_post_incr_str();
return (is_post_incr) ? "!" : "";
endfunction : get_post_incr_str

// `include "isa/riscv_instr_cov.svh"

endclass
4 changes: 2 additions & 2 deletions cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr_enum.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -35,8 +35,8 @@
CV_CLB,
CV_CNT,
CV_ABS,
CV_SLET,
CV_SLETU,
CV_SLE,
CV_SLEU,
CV_MIN,
CV_MINU,
CV_MAX,
Expand Down
102 changes: 51 additions & 51 deletions cv32e40p/env/corev-dv/custom/isa/custom/rv32x_instr.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -18,11 +18,11 @@
`DEFINE_CV32E40P_INSTR(CV_BNEIMM , B_FORMAT, BRANCH_IMM, RV32X)

// HW LOOPS
`DEFINE_CV32E40P_INSTR(CV_START , I_FORMAT, HWLOOP, RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_START , I_FORMAT, HWLOOP, RV32X)
`DEFINE_CV32E40P_INSTR(CV_STARTI, I_FORMAT, HWLOOP, RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_END , I_FORMAT, HWLOOP, RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_END , I_FORMAT, HWLOOP, RV32X)
`DEFINE_CV32E40P_INSTR(CV_ENDI , I_FORMAT, HWLOOP, RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_COUNT , I_FORMAT, HWLOOP, RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_COUNT , I_FORMAT, HWLOOP, RV32X)
`DEFINE_CV32E40P_INSTR(CV_COUNTI, I_FORMAT, HWLOOP, RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_SETUP , I_FORMAT, HWLOOP, RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_SETUPI, I_FORMAT, HWLOOP, RV32X, UIMM)
Expand All @@ -47,8 +47,8 @@

// ALU
`DEFINE_CV32E40P_INSTR(CV_ABS , R_FORMAT , ALU , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SLET , R_FORMAT , ALU , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SLETU , R_FORMAT , ALU , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SLE , R_FORMAT , ALU , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SLEU , R_FORMAT , ALU , RV32X)
`DEFINE_CV32E40P_INSTR(CV_MIN , R_FORMAT , ALU , RV32X)
`DEFINE_CV32E40P_INSTR(CV_MINU , R_FORMAT , ALU , RV32X)
`DEFINE_CV32E40P_INSTR(CV_MAX , R_FORMAT , ALU , RV32X)
Expand Down Expand Up @@ -121,18 +121,18 @@
`DEFINE_CV32E40P_INSTR(CV_AVGU_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_AVGU_SC_H , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_AVGU_SC_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_AVGU_SCI_H , I_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_AVGU_SCI_B , I_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_AVGU_SCI_H , I_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_AVGU_SCI_B , I_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_MIN_H , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_MIN_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_MIN_SC_H , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_MIN_SC_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_MIN_SCI_H , I_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_MIN_SCI_B , I_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_MINU_H , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_MINU_B , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_MINU_SC_H , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_MINU_SC_B , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_MINU_H , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_MINU_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_MINU_SC_H , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_MINU_SC_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_MINU_SCI_H , I_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_MINU_SCI_B , I_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_MAX_H , R_FORMAT , SIMD , RV32X)
Expand All @@ -141,30 +141,30 @@
`DEFINE_CV32E40P_INSTR(CV_MAX_SC_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_MAX_SCI_H , I_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_MAX_SCI_B , I_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_MAXU_H , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_MAXU_B , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_MAXU_SC_H , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_MAXU_SC_B , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_MAXU_H , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_MAXU_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_MAXU_SC_H , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_MAXU_SC_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_MAXU_SCI_H , I_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_MAXU_SCI_B , I_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_SRL_H , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SRL_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SRL_SC_H , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SRL_SC_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SRL_SCI_H , I_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SRL_SCI_B , I_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SRL_SCI_H , I_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_SRL_SCI_B , I_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_SRA_H , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SRA_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SRA_SC_H , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SRA_SC_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SRA_SCI_H , I_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SRA_SCI_B , I_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SRA_SCI_H , I_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_SRA_SCI_B , I_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_SLL_H , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SLL_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SLL_SC_H , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SLL_SC_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SLL_SCI_H , I_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SLL_SCI_B , I_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SLL_SCI_H , I_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_SLL_SCI_B , I_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_OR_H , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_OR_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_OR_SC_H , R_FORMAT , SIMD , RV32X)
Expand All @@ -185,10 +185,10 @@
`DEFINE_CV32E40P_INSTR(CV_AND_SCI_B , I_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_ABS_H , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_ABS_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_DOTUP_H , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_DOTUP_B , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_DOTUP_SC_H , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_DOTUP_SC_B , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_DOTUP_H , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_DOTUP_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_DOTUP_SC_H , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_DOTUP_SC_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_DOTUP_SCI_H , I_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_DOTUP_SCI_B , I_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_DOTUSP_H , R_FORMAT , SIMD , RV32X)
Expand All @@ -203,10 +203,10 @@
`DEFINE_CV32E40P_INSTR(CV_DOTSP_SC_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_DOTSP_SCI_H , I_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_DOTSP_SCI_B , I_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SDOTUP_H , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_SDOTUP_B , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_SDOTUP_SC_H , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_SDOTUP_SC_B , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_SDOTUP_H , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SDOTUP_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SDOTUP_SC_H , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SDOTUP_SC_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SDOTUP_SCI_H , I_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_SDOTUP_SCI_B , I_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_SDOTUSP_H , R_FORMAT , SIMD , RV32X)
Expand All @@ -221,12 +221,12 @@
`DEFINE_CV32E40P_INSTR(CV_SDOTSP_SC_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SDOTSP_SCI_H , I_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SDOTSP_SCI_B , I_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_EXTRACT_H , I_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_EXTRACT_B , I_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_EXTRACTU_H , I_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_EXTRACTU_B , I_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_INSERT_H , I_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_INSERT_B , I_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_EXTRACT_H , I_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_EXTRACT_B , I_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_EXTRACTU_H , I_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_EXTRACTU_B , I_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_INSERT_H , I_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_INSERT_B , I_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_SHUFFLE_H , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SHUFFLE_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_SHUFFLE_SCI_H , I_FORMAT , SIMD , RV32X, UIMM)
Expand Down Expand Up @@ -276,28 +276,28 @@
`DEFINE_CV32E40P_INSTR(CV_CMPLE_SC_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_CMPLE_SCI_H , I_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_CMPLE_SCI_B , I_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_CMPGTU_H , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_CMPGTU_B , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_CMPGTU_SC_H , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_CMPGTU_SC_B , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_CMPGTU_H , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_CMPGTU_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_CMPGTU_SC_H , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_CMPGTU_SC_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_CMPGTU_SCI_H , I_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_CMPGTU_SCI_B , I_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_CMPGEU_H , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_CMPGEU_B , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_CMPGEU_SC_H , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_CMPGEU_SC_B , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_CMPGEU_H , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_CMPGEU_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_CMPGEU_SC_H , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_CMPGEU_SC_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_CMPGEU_SCI_H , I_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_CMPGEU_SCI_B , I_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_CMPLTU_H , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_CMPLTU_B , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_CMPLTU_SC_H , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_CMPLTU_SC_B , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_CMPLTU_H , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_CMPLTU_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_CMPLTU_SC_H , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_CMPLTU_SC_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_CMPLTU_SCI_H , I_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_CMPLTU_SCI_B , I_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_CMPLEU_H , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_CMPLEU_B , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_CMPLEU_SC_H , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_CMPLEU_SC_B , R_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_CMPLEU_H , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_CMPLEU_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_CMPLEU_SC_H , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_CMPLEU_SC_B , R_FORMAT , SIMD , RV32X)
`DEFINE_CV32E40P_INSTR(CV_CMPLEU_SCI_H , I_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_CMPLEU_SCI_B , I_FORMAT , SIMD , RV32X, UIMM)
`DEFINE_CV32E40P_INSTR(CV_CPLXMUL_R , R_FORMAT , SIMD , RV32X)
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