Merge pull request #2380 from XavierAubert/cv32e40p/dev_dd_w9a

Coverage analysis update and new regress features for shell script generation

bin/lib/cv_regression.py

@@ -89,9 +89,6 @@ def __init__(self, **kwargs):
         if not hasattr(self, 'testname'):
             self.testname = self.name
 
-        if not hasattr(self, 'riscvdv_cfg'):
-            self.riscvdv_cfg = ''
-
         # Log equals the test name if does not exist
         if not hasattr(self, 'log'):
             self.log = self.name

bin/templates/regress_sh.j2

@@ -105,8 +105,12 @@ popd > /dev/null
 {% else %}
   {% set test_cfg = "" %}
 {% endif %}
+{% set test_cfg_list = test_cfg|replace(" ",",")|replace("+",",") %}
+{% set test_cfg_list = test_cfg_list.split(",")|unique|sort %}
+{% set test_cfg_path = test_cfg_list|join("__") %}
+
 # --> Test (Index: {{run_index}}): {{t.cmd}} : {{t.description}}
-{% set cmd = test_cmd + ' CV_CORE=' + project + ' CFG=' + r.builds[build].cfg + ' ' + toolchain|upper + '=1' + ' RISCVDV_CFG=' + t.riscvdv_cfg + ' SIMULATOR=' + t.simulator + ' COMP=0 USE_ISS=' + regress_macros.yesorno(t.iss) + ' COV=' + regress_macros.yesorno(t.cov) + ' SEED=random GEN_START_INDEX=' + run_index|string + ' RUN_INDEX=' + run_index|string + ' TEST_CFG_FILE=' + test_cfg + ' ' + regress_macros.cv_results(results) + ' ' + makeargs %}
+{% set cmd = test_cmd + ' CV_CORE=' + project + ' CFG=' + r.builds[build].cfg + ' ' + toolchain|upper + '=1 SIMULATOR=' + t.simulator + ' COMP=0 USE_ISS=' + regress_macros.yesorno(t.iss) + ' COV=' + regress_macros.yesorno(t.cov) + ' SEED=random GEN_START_INDEX=' + run_index|string + ' RUN_INDEX=' + run_index|string + ' TEST_CFG_FILE=\"' + test_cfg + '\" ' + regress_macros.cv_results(results) + ' ' + makeargs %}
 echo "{{session}}: Running test [cd {{t.abs_dir}} && {{cmd}}]"
 pushd {{t.abs_dir}} > /dev/null
 {{cmd}} >& /dev/null;
@@ -119,11 +123,6 @@ popd > /dev/null
 {% set results_dir = t.simulator + '_results' %}
 {% endif %}
 {% set sim_log = t.simulator + '-' + test_log + '.log' %}
-{% if t.test_cfg is defined %}
-  {% set test_cfg_path = t.test_cfg %}
-{% else %}
-  {% set test_cfg_path = '' %}
-{% endif %}
 
 {# Determine log location #}
 {% if t.results %}

bin/templates/regress_vsif.j2

@@ -64,7 +64,7 @@ group {{project}} {
         test precmd {
             sv_seed: gen_random;
             count: 1;
-            run_script: 'cd {{t.abs_dir}} && {{t.precmd}} CV_SIM_PREFIX= CV_CORE={{project}} CFG={{build.cfg}} RISCVDV_CFG={{t.riscvdv_cfg}} {{toolchain|upper}}=1 SIMULATOR={{t.simulator}} RNDSEED=$RUN_ENV(BRUN_SV_SEED) NUM_TESTS={{t.num}} {{regress_macros.cv_results(results)}} {{makeargs}}';
+            run_script: 'cd {{t.abs_dir}} && {{t.precmd}} CV_SIM_PREFIX= CV_CORE={{project}} CFG={{build.cfg}} {{toolchain|upper}}=1 SIMULATOR={{t.simulator}} RNDSEED=$RUN_ENV(BRUN_SV_SEED) NUM_TESTS={{t.num}} {{regress_macros.cv_results(results)}} {{makeargs}}';
         };
 {% else %}
 {% endif %}

cv32e40p/env/corev-dv/cv32e40p_instr_sequence.sv

@@ -210,7 +210,7 @@ class cv32e40p_instr_sequence extends riscv_instr_sequence;
         end
         instr_stream.instr_list[i].has_label = 1'b1;
       end else begin
-        if(instr_stream.instr_list[i].has_label) begin
+        if(instr_stream.instr_list[i].has_label) begin : HAS_LABEL
           //check if it is hwloop label
           label_is_pulp_hwloop_body_label = check_str_pattern_match(instr_stream.instr_list[i].label, "hwloop");
           if(!label_is_pulp_hwloop_body_label) begin
@@ -265,14 +265,26 @@ class cv32e40p_instr_sequence extends riscv_instr_sequence;
               format_str_len = LABEL_STR_LEN;
             end
           end
-        end else begin
+          str = {prefix, instr_stream.instr_list[i].convert2asm()};
+        end // HAS_LABEL
+        else if (instr_stream.instr_list[i].is_illegal_instr) begin : IS_ILLEGAL_INSTR
+          // insert illegal insn in directed stream
+          cv32_illegal_instr.init(cfg);
+          cv32_illegal_instr.cv32e40p_init(cfg); // Init legal_opcode for cv32e40p
+          `DV_CHECK_RANDOMIZE_WITH_FATAL(cv32_illegal_instr, exception != kHintInstr;)
+          str = {indent, $sformatf(".4byte 0x%s # %0s", cv32_illegal_instr.get_bin_str(), cv32_illegal_instr.comment)};
+        end // IS_ILLEGAL_INSTR
+        else begin
           prefix = format_string(" ", format_str_len);
+          str = {prefix, instr_stream.instr_list[i].convert2asm()};
         end
-      end
-      str = {prefix, instr_stream.instr_list[i].convert2asm()};
+      end // i != 0
+
+      // str = {prefix, instr_stream.instr_list[i].convert2asm()};
       instr_string_list.push_back(str);
 
-    end
+    end // instr_stream.instr_list.size
+
     // If PMP is supported, need to align <main> to a 4-byte boundary.
     if (riscv_instr_pkg::support_pmp && !uvm_re_match(uvm_glob_to_re("*main*"), label_name)) begin
       instr_string_list.push_front(".align 2");

cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv

@@ -53,6 +53,7 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream;
   bit                         use_prev_rd_on_next_operands;       // previous instr rd is used for directed instr operands
   bit                         use_diff_regs_for_operands = 0;     // to control rand instr uses different registers for instr oeprands
   bit                         more_weight_for_fdiv_fsqrt_gen;     // more weight on generating fdiv and fsqrt directed_instr
+  bit                         use_only_for_fdiv_fsqrt_gen;        // use only fdiv and fsqrt directed_instr
   bit                         init_gpr = (is_zfinx) ? 1 : 0;      // initialize gpr registers in stream with rand value
   bit                         init_fpr = (is_zfinx) ? 0 : 1;      // initialize fpr registers in stream with rand value
   bit                         en_clr_fflags_af_instr;             // clear fflag to prevent residual fflags status of current f_instr
@@ -415,9 +416,9 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream;
       end
     end
 
-    if (more_weight_for_fdiv_fsqrt_gen) begin
+    if (more_weight_for_fdiv_fsqrt_gen || use_only_for_fdiv_fsqrt_gen) begin
       if (select_fp_instr) // is fp
-        if ($urandom_range(1)) // 50% rate of getting fdiv/fsqrt
+        if ($urandom_range(1) || use_only_for_fdiv_fsqrt_gen)
           include_instr = new[1] ($urandom_range(1) ? {FDIV_S} : {FSQRT_S});
     end
 
@@ -830,6 +831,17 @@ class cv32e40p_float_zfinx_base_instr_stream extends cv32e40p_base_instr_stream;
       instr_list[$].comment = {instr_list[$].comment, $sformatf(" [WFI Insertion] ")};
   endfunction: insert_wfi_instr
 
+  // add illegal
+  virtual function void insert_illegal_instr();
+      riscv_instr illegal_instr;
+      illegal_instr = new riscv_instr::get_rand_instr(
+        .include_instr({NOP}) // create a placholder insn
+      );
+      illegal_instr.is_illegal_instr = 1; // tag this as illegal 
+      instr_list.push_back(illegal_instr);
+      instr_list[$].comment = {instr_list[$].comment, $sformatf(" [Illegal Insertion] ")};
+  endfunction: insert_illegal_instr
+
   // for overriding direct instr operands with previous instruc rd/fd
   virtual function void f_use_prev_rd_on_next_operands(
     riscv_instr                 p_instr=null,

cv32e40p/env/corev-dv/instr_lib/cv32e40p_instr_for_func_cvg_lib.sv

@@ -1,5 +1,5 @@
 /*
- * Copyright 2023 Dolphin Design
+ * Copyright 2024 Dolphin Design
  * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -16,7 +16,9 @@
  */
 
 // [Dolphin Design updates]
-// This file contains stream classes that use to generate streams that improve functional coverage holes
+// Note:
+// 1) This file contains streams that use to improve functional coverage holes
+// 2) They are optional to be included in regression list
 
 // this stream is to improve func coverage for in uvme_interrupt_covg_v2 by cycle through all cv_* instructions multiple times for irq and wfi coverage purpose - START
 class cv32e40p_cv_instrs_multi_loops_streams extends cv32e40p_float_zfinx_base_instr_stream;
@@ -43,7 +45,7 @@ class cv32e40p_cv_instrs_multi_loops_streams extends cv32e40p_float_zfinx_base_i
     reset_rand_instr_entry();
 
     include_group   = new[1] ({RV32X});
-    exclude_instr   = new[9] ({CV_START, CV_STARTI, CV_END, CV_ENDI, CV_COUNT, CV_COUNTI, CV_SETUP, CV_SETUPI, CV_ELW}); // TBD: exclude hwloop and cluster insn from wfi cg
+    exclude_instr   = new[9] ({CV_START, CV_STARTI, CV_END, CV_ENDI, CV_COUNT, CV_COUNTI, CV_SETUP, CV_SETUPI, CV_ELW});
 
     // these already covered in all cvg, can be ignored meantime - Start (note: users can modify this to focus on insn list to b ecovered)
     ignored_instr_cnt = 4;
@@ -181,3 +183,67 @@ class cv32e40p_cv_instrs_w_wfi_multi_loops_streams extends cv32e40p_cv_instrs_mu
 endclass: cv32e40p_cv_instrs_w_wfi_multi_loops_streams
 // this stream is to improve func coverage for in uvme_interrupt_covg_v2 by cycle through all cv_* instructions multiple times for irq and wfi coverage purpose - END
 
+
+// this stream is to improve func coverage for in uvme_rv32x_hwloop_covg - START
+class cv32e40p_xpulp_single_hwloop_stream_directed extends cv32e40p_xpulp_hwloop_base_stream;
+
+  `uvm_object_utils(cv32e40p_xpulp_single_hwloop_stream_directed)
+  `uvm_object_new
+
+  constraint gen_hwloop_count_c {
+    solve num_loops_active before gen_nested_loop;
+    solve gen_nested_loop  before hwloop_count, hwloop_counti;
+    solve num_hwloop_instr before hwloop_count, hwloop_counti;
+    gen_nested_loop == 0;
+    num_loops_active == 1;
+    foreach(hwloop_count[i]) {
+      if (num_hwloop_instr[i] == 3) {
+        hwloop_count[i]  == 4095;
+      }
+      else {
+        hwloop_count[i]  inside {401, 1024};
+      }
+      hwloop_counti[i] == hwloop_count[i];
+    }
+  }
+
+  constraint no_imm_hwloop_setup_instr_c {
+      use_loop_counti_inst[0] == 0;
+      use_loop_counti_inst[1] == 0;
+      use_loop_setupi_inst[0] == 0;
+      use_loop_setupi_inst[1] == 0;
+  }
+
+  constraint num_hwloop_instr_c {
+    foreach (num_hwloop_instr[i]) {
+      num_hwloop_instr[i] dist { 3 := 1, 3074 := 5, 4092 := 1 };
+      num_fill_instr_loop_ctrl_to_loop_start[i] inside {[0:7]};
+    }
+    num_fill_instr_in_loop1_till_loop0_setup == 0;
+  }
+
+endclass : cv32e40p_xpulp_single_hwloop_stream_directed
+// this stream is to improve func coverage for in uvme_rv32x_hwloop_covg - END
+
+// this stream is to improve func coverage for in uvme_debug_covg - START
+class cv32e40p_fp_only_fdiv_fsqrt_stream extends cv32e40p_fp_n_mixed_instr_stream;
+
+  `uvm_object_utils(cv32e40p_fp_only_fdiv_fsqrt_stream)
+  `uvm_object_new
+
+  function void pre_randomize();
+    super.pre_randomize();
+    use_fp_only_for_directed_instr  = 1;
+    use_only_for_fdiv_fsqrt_gen     = 1;
+    en_clr_fflags_af_instr          = 0;
+  endfunction: pre_randomize
+
+  virtual function void add_instr_prior_directed_instr(riscv_instr instr, int idx=0);
+    if ($test$plusargs("add_b2b_illegal_insn")) begin
+      insert_illegal_instr();
+    end
+    super.add_instr_prior_directed_instr(instr, idx);
+  endfunction : add_instr_prior_directed_instr
+
+endclass: cv32e40p_fp_only_fdiv_fsqrt_stream
+// this stream is to improve func coverage for in uvme_debug_covg - END

cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv

@@ -505,8 +505,9 @@ class cv32e40p_xpulp_hwloop_base_stream extends cv32e40p_xpulp_rand_stream;
 
               num_fill_instr_in_loop1_till_loop0_setup = num_fill_instr_in_loop1_till_loop0_setup-1;
 
-              if(num_fill_instr_in_loop1_till_loop0_setup>0)
+              if(num_fill_instr_in_loop1_till_loop0_setup>0) begin
                   insert_rand_instr(num_fill_instr_in_loop1_till_loop0_setup);
+              end
           end
           else begin
               set_label_at_next_instr = 1; //no fill instr so next instr must have label
@@ -536,8 +537,9 @@ class cv32e40p_xpulp_hwloop_base_stream extends cv32e40p_xpulp_rand_stream;
 
           //reserved_rd = {hwloop_avail_regs[2]}; //preserve count0 reg for nested loop
 
-          if(!use_setup_inst[0])
+            if(!use_setup_inst[0]) begin
               insert_rand_instr(num_fill_instr_loop_ctrl_to_loop_start[0]);
+            end
 
           //LABEL HWLOOP0_NESTED_START:
           label_s = $sformatf("hwloop0_nested_start_stream%0d",stream_count);
@@ -1283,21 +1285,21 @@ class cv32e40p_xpulp_short_hwloop_stream_directed extends cv32e40p_xpulp_short_h
       //  due to long run times
       if(gen_nested_loop) {
         if(loop0_high_count) {
-          hwloop_counti[0] dist {[1024:4094] := 50, 4095 := 5};
-          hwloop_count[0]  dist {[1024:4094] := 50, 4095 := 5};
+          hwloop_counti[0] dist {[1024:4094] := 15, 4095 := 5};
+          hwloop_count[0]  dist {[1024:4094] := 15, 4095 := 5};
           hwloop_counti[1] inside {[1:2]};
           hwloop_count[1]  inside {[1:2]};
         } else {
           hwloop_counti[0] inside {[1:2]};
           hwloop_count[0]  inside {[1:2]};
-          hwloop_counti[1] dist {[1024:4094] := 50, 4095 := 5};
-          hwloop_count[1]  dist {[1024:4094] := 50, 4095 := 5};
+          hwloop_counti[1] dist {[1024:4094] := 15, 4095 := 5};
+          hwloop_count[1]  dist {[1024:4094] := 15, 4095 := 5};
         }
       } else {
         foreach(hwloop_counti[i])
-          hwloop_counti[i] dist {[1024:4094] := 50, 4095 := 5};
+          hwloop_counti[i] dist {[1024:4094] := 15, 4095 := 5};
         foreach(hwloop_count[i])
-          hwloop_count[i]  dist {[1024:4094] := 50, 4095 := 5};
+          hwloop_count[i]  dist {[1024:4094] := 15, 4095 := 5};
       }
   }
 

cv32e40p/env/uvme/cov/uvme_debug_covg.sv

@@ -288,11 +288,11 @@ class uvme_debug_covg extends uvm_component;
         }
         dreq_and_ill : cross dreq, ill;
         irq_and_dreq : cross dreq, irq;
-        irq_dreq_trig_ill : cross dreq, irq, trigger, ill;
-        irq_dreq_trig_cebreak : cross dreq, irq, trigger, cebreak;
-        irq_dreq_trig_ebreak : cross dreq, irq, trigger, ebreak;
-        irq_dreq_trig_branch : cross dreq, irq, trigger, branch;
-        irq_dreq_trig_multicycle : cross dreq, irq, trigger, mulhsu;
+        irq_dreq_trig_ill : cross dreq, irq, trigger, ill; // irq + haltreq + trigger (illegal)
+        irq_dreq_trig_cebreak : cross dreq, irq, trigger, cebreak; // irq + haltreq + trigger (cbreak)
+        irq_dreq_trig_ebreak : cross dreq, irq, trigger, ebreak; // irq + haltreq + trigger (ebreak)
+        irq_dreq_trig_branch : cross dreq, irq, trigger, branch; // irq + haltreq + trigger (branch)
+        irq_dreq_trig_multicycle : cross dreq, irq, trigger, mulhsu; // irq + haltreq + trigger (mc)
     endgroup
 
     // Cover access to dcsr, dpc and dscratch0/1 in D-mode
@@ -529,8 +529,39 @@ class uvme_debug_covg extends uvm_component;
         cr_dbg_while_multi_cyc_f_B : cross cp_apu_busy, cp_dbg_req;
 
         // debug_halt_req with irq during multi cycle fp inst
-        cr_dbg_irq_while_multi_cyc_f_A : cross cp_apu_req_valid, cp_apu_grant_valid, cp_dbg_req, cp_irq;
-        cr_dbg_irq_while_multi_cyc_f_B : cross cp_apu_busy, cp_dbg_req, cp_irq;
+        cr_dbg_irq_while_multi_cyc_f_A : cross cp_apu_req_valid, cp_apu_grant_valid, cp_dbg_req, cp_irq {
+          bins irq_grp_upper16_multi_cyc_f_A = binsof(cp_dbg_req.dbg_req_active) && binsof(cp_apu_grant_valid) && (
+                                 binsof(cp_irq.irq_31_trans_0_to_1) || binsof(cp_irq.irq_30_trans_0_to_1) ||
+                                 binsof(cp_irq.irq_29_trans_0_to_1) || binsof(cp_irq.irq_28_trans_0_to_1) ||
+                                 binsof(cp_irq.irq_27_trans_0_to_1) || binsof(cp_irq.irq_26_trans_0_to_1) ||
+                                 binsof(cp_irq.irq_25_trans_0_to_1) || binsof(cp_irq.irq_24_trans_0_to_1) ||
+                                 binsof(cp_irq.irq_23_trans_0_to_1) || binsof(cp_irq.irq_22_trans_0_to_1) ||
+                                 binsof(cp_irq.irq_21_trans_0_to_1) || binsof(cp_irq.irq_20_trans_0_to_1) ||
+                                 binsof(cp_irq.irq_19_trans_0_to_1) || binsof(cp_irq.irq_18_trans_0_to_1) ||
+                                 binsof(cp_irq.irq_17_trans_0_to_1) || binsof(cp_irq.irq_16_trans_0_to_1));
+          bins irq_grp_lower16_multi_cyc_f_A = binsof(cp_dbg_req.dbg_req_active) && binsof(cp_apu_grant_valid) && (
+                                 binsof(cp_irq.irq_11_trans_0_to_1) || 
+                                 binsof(cp_irq.irq_3_trans_0_to_1)  ||
+                                 binsof(cp_irq.irq_7_trans_0_to_1));
+          ignore_bins dbg_req_others = binsof(cp_dbg_req.dbg_req_0_to_1);
+        }
+        cr_dbg_irq_while_multi_cyc_f_B : cross cp_apu_busy, cp_dbg_req, cp_irq {
+          bins irq_grp_upper16_multi_cyc_f_B = binsof(cp_dbg_req.dbg_req_active) && (binsof(cp_apu_busy.apu_busy) intersect {1}) && (
+                                 binsof(cp_irq.irq_31_trans_0_to_1) || binsof(cp_irq.irq_30_trans_0_to_1) ||
+                                 binsof(cp_irq.irq_29_trans_0_to_1) || binsof(cp_irq.irq_28_trans_0_to_1) ||
+                                 binsof(cp_irq.irq_27_trans_0_to_1) || binsof(cp_irq.irq_26_trans_0_to_1) ||
+                                 binsof(cp_irq.irq_25_trans_0_to_1) || binsof(cp_irq.irq_24_trans_0_to_1) ||
+                                 binsof(cp_irq.irq_23_trans_0_to_1) || binsof(cp_irq.irq_22_trans_0_to_1) ||
+                                 binsof(cp_irq.irq_21_trans_0_to_1) || binsof(cp_irq.irq_20_trans_0_to_1) ||
+                                 binsof(cp_irq.irq_19_trans_0_to_1) || binsof(cp_irq.irq_18_trans_0_to_1) ||
+                                 binsof(cp_irq.irq_17_trans_0_to_1) || binsof(cp_irq.irq_16_trans_0_to_1));
+          bins irq_grp_lower16_multi_cyc_f_B = binsof(cp_dbg_req.dbg_req_active) && (binsof(cp_apu_busy.apu_busy) intersect {1}) && (
+                                 binsof(cp_irq.irq_11_trans_0_to_1) || 
+                                 binsof(cp_irq.irq_3_trans_0_to_1) ||
+                                 binsof(cp_irq.irq_7_trans_0_to_1));
+          ignore_bins dbg_apu_busy_others = (binsof(cp_apu_busy.apu_busy) intersect {0}) || binsof(cp_apu_busy.apu_busy_0_to_1) || binsof(cp_apu_busy.apu_busy_1_to_0);
+          ignore_bins dbg_req_others = binsof(cp_dbg_req.dbg_req_0_to_1);
+        }
 
         // debug_halt_req with illegal instr during multi cycle fp inst
         cr_dbg_ill_while_multi_cyc_f_A : cross cp_apu_req_valid, cp_apu_grant_valid, cp_dbg_req, cp_ill;

cv32e40p/env/uvme/cov/uvme_interrupt_covg_v2.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////////////////////////////////////////
 //
 // Copyright 2023 OpenHW Group
-// Copyright 2023 Dolphin Design
+// Copyright 2024 Dolphin Design
 //
 // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.