Merge pull request #2421 from XavierAubert/cv32e40p/dev_bnl_ww18_PR

CV32E40Pv2 Verification update Week 18 PR

cv32e40p/env/corev-dv/cv32e40p_instr_test_pkg.sv

@@ -118,19 +118,24 @@ package cv32e40p_instr_test_pkg;
   // Push general purpose register to the debugger stack
   function automatic void push_gpr_to_debugger_stack(cv32e40p_instr_gen_config cfg_corev,
                                                      ref string instr[$]);
-    string store_instr = (XLEN == 32) ? "sw" : "sd";
+    string        store_instr = (XLEN == 32) ? "sw" : "sd";
+    bit           done_store_mscratch = 1'b0;
+    int unsigned  total_gpr = 32;
     // Reserve space from debugger stack to save all 32 GPR except for x0 + MSCRATCH
     instr.push_back($sformatf("1: addi x%0d, x%0d, -%0d", cfg_corev.dp, cfg_corev.dp, 32 * (XLEN/8)));
     // Push all GPRs to debugger stack
-    for(int i = 1; i < 32; i++) begin
+    for(int i = 1; i < total_gpr; i++) begin
       if (i == cfg_corev.dp) continue;
       if (i == cfg_corev.sp) continue;
       if (i == cfg_corev.tp) continue;
       instr.push_back($sformatf("%0s  x%0d, %0d(x%0d)", store_instr, i, (i-1) * (XLEN/8), cfg_corev.dp));
+      if (!done_store_mscratch) begin
+        // Read and Push MSCRATCH to debugger stack
+        instr.push_back($sformatf("csrrw x%0d, 0x340, x%0d # MSCRATCH", i, i));
+        instr.push_back($sformatf("%0s  x%0d, %0d(x%0d)", store_instr, i, (total_gpr-1) * (XLEN/8), cfg_corev.dp));
+        done_store_mscratch = 1;
+      end
     end
-    // Read and Push MSCRATCH to debugger stack
-    instr.push_back($sformatf("csrrw x5, 0x340, x5 # MSCRATCH"));
-    instr.push_back($sformatf("%0s  x%0d, %0d(x%0d)", store_instr, 5, 31 * (XLEN/8), cfg_corev.dp));
   endfunction : push_gpr_to_debugger_stack
 
   // Push floating point registers to the debugger stack
@@ -212,17 +217,22 @@ package cv32e40p_instr_test_pkg;
   // Pop general purpose register from debugger stack
   function automatic void pop_gpr_from_debugger_stack(cv32e40p_instr_gen_config cfg_corev,
                                                       ref string instr[$]);
-    string load_instr = (XLEN == 32) ? "lw" : "ld";
+    string        load_instr = (XLEN == 32) ? "lw" : "ld";
+    bit           done_load_mscratch = 1'b0;
+    int unsigned  total_gpr = 32;
     // Pop user mode GPRs from kernel stack
-    for(int i = 1; i < 32; i++) begin
+    for(int i = 1; i < total_gpr; i++) begin
       if (i == cfg_corev.dp) continue;
       if (i == cfg_corev.sp) continue;
       if (i == cfg_corev.tp) continue;
+      if (!done_load_mscratch) begin
+        // Pop and Write MSCRATCH from debugger stack
+        instr.push_back($sformatf("%0s  x%0d, %0d(x%0d)", load_instr, i, (total_gpr-1) * (XLEN/8), cfg_corev.dp));
+        instr.push_back($sformatf("csrrw x%0d, 0x340, x%0d # MSCRATCH", i, i));
+        done_load_mscratch = 1;
+      end
       instr.push_back($sformatf("%0s  x%0d, %0d(x%0d)", load_instr, i, (i-1) * (XLEN/8), cfg_corev.dp));
     end
-    // Pop and Write MSCRATCH from debugger stack
-    instr.push_back($sformatf("%0s  x%0d, %0d(x%0d)", load_instr, 5, 31 * (XLEN/8), cfg_corev.dp));
-    instr.push_back($sformatf("csrrw x5, 0x340, x5 # MSCRATCH"));
     // Restore debugger stack pointer
     instr.push_back($sformatf("addi x%0d, x%0d, %0d", cfg_corev.dp, cfg_corev.dp, 31 * (XLEN/8)));
   endfunction : pop_gpr_from_debugger_stack

cv32e40p/regress/cv32e40pv2_legacy_v1.yaml

@@ -157,17 +157,51 @@ tests:
     dir: cv32e40p/sim/uvmt
     cmd: make test COREV=YES TEST=matmul_32b_int CFG_PLUSARGS="+UVM_TIMEOUT=30000000"
 
+  # Can only run with num_mhpmcounter_29 configuration
   mhpmcounter29_csr_access_test_1:
-    build: uvmt_cv32e40p
+    build: uvmt_cv32e40p_num_mhpmcounter_29
     description: mhpmcounter29_csr_access_test_1
     dir: cv32e40p/sim/uvmt
     cmd: make test COREV=YES TEST=mhpmcounter29_csr_access_test_1 CFG_PLUSARGS="+UVM_TIMEOUT=30000000"
-
+    skip_sim: default
+              no_pulp
+              pulp
+              pulp_fpu
+              pulp_fpu_1cyclat
+              pulp_fpu_2cyclat
+              pulp_fpu_zfinx
+              pulp_fpu_zfinx_1cyclat
+              pulp_fpu_zfinx_2cyclat
+              pulp_cluster
+              pulp_cluster_fpu
+              pulp_cluster_fpu_1cyclat
+              pulp_cluster_fpu_2cyclat
+              pulp_cluster_fpu_zfinx
+              pulp_cluster_fpu_zfinx_1cyclat
+              pulp_cluster_fpu_zfinx_2cyclat
+
+  # Can only run with num_mhpmcounter_29 configuration
   mhpmcounter29_csr_access_test_2:
-    build: uvmt_cv32e40p
+    build: uvmt_cv32e40p_num_mhpmcounter_29
     description: mhpmcounter29_csr_access_test_2
     dir: cv32e40p/sim/uvmt
     cmd: make test COREV=YES TEST=mhpmcounter29_csr_access_test_2 CFG_PLUSARGS="+UVM_TIMEOUT=30000000"
+    skip_sim: default
+              no_pulp
+              pulp
+              pulp_fpu
+              pulp_fpu_1cyclat
+              pulp_fpu_2cyclat
+              pulp_fpu_zfinx
+              pulp_fpu_zfinx_1cyclat
+              pulp_fpu_zfinx_2cyclat
+              pulp_cluster
+              pulp_cluster_fpu
+              pulp_cluster_fpu_1cyclat
+              pulp_cluster_fpu_2cyclat
+              pulp_cluster_fpu_zfinx
+              pulp_cluster_fpu_zfinx_1cyclat
+              pulp_cluster_fpu_zfinx_2cyclat
 
   misalign:
     build: uvmt_cv32e40p

cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml

@@ -140,18 +140,13 @@ tests:
     dir: cv32e40p/sim/uvmt
     cmd: make test COREV=YES TEST=pulp_hardware_loop_debug_test
     num: 1
-    skip_sim:
-      - pulp
-      - pulp_fpu
-      - pulp_fpu_1cyclat
-      - pulp_fpu_2cyclat
-      - pulp_cluster
-      - pulp_cluster_fpu
-      - pulp_cluster_fpu_1cyclat
-      - pulp_cluster_fpu_2cyclat
-      - default
-      - no_pulp
 
+  debug_hwloop_test:
+    build: uvmt_cv32e40p
+    description: debug_hwloop_test directed test
+    dir: cv32e40p/sim/uvmt
+    cmd: make test COREV=YES TEST=debug_hwloop_test
+    num: 1
 
 # ====================================================================================
 # V1 legacy pulp tests

cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do

@@ -25,7 +25,6 @@ coverage exclude -line 140 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb
 coverage exclude -line 142 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.}
 coverage exclude -line 144 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.}
 coverage exclude -line 1047 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/cs_registers_i/gen_no_pulp_secure_write_logic -comment {Never save exception pc in ex because no data error from PMP.}
-coverage exclude -line 1105 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/cs_registers_i -comment {u_irq_enable_o never asserted. mstatus.uie never enabled.}
 coverage exclude -line 1047 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/cs_registers_i/gen_no_pulp_secure_write_logic -comment {Never save exception pc in ex because no data error from PMP.}
 coverage exclude -line 1048 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/cs_registers_i/gen_no_pulp_secure_write_logic -comment {Default of unique case not covered}
 coverage exclude -line 134 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i -comment {We dont use USER mode.}
@@ -34,16 +33,7 @@ coverage exclude -line 165 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb
 coverage exclude -line 134 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i -comment {We dont use USER mode.}
 coverage exclude -line 140 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i -comment {We dont use USER mode.}
 coverage exclude -line 165 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i -comment {We dont use USER mode.}
-coverage exclude -line 113 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never fetch_valid == 0 when if_valid == 1. This case is impossible to reach since if_valid depends on fetch_valid to be asserted.}
-coverage exclude -line 125 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never fetch_valid == 0 when if_valid == 1. This case is impossible to reach since if_valid depends on fetch_valid to be asserted.}
-coverage exclude -line 141 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never fetch_valid == 0 when if_valid == 1. This case is impossible to reach since if_valid depends on fetch_valid to be asserted.}
-coverage exclude -line 201 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never fetch_valid == 0 when if_valid == 1. This case is impossible to reach since if_valid depends on fetch_valid to be asserted.}
-coverage exclude -line 212 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never fetch_valid == 0 when if_valid == 1. This case is impossible to reach since if_valid depends on fetch_valid to be asserted.}
-coverage exclude -line 163 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never aligner_ready when entering misaligned 16 state. Always fetch valid the cycle before.}
-coverage exclude -line 174 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never aligner_ready when entering misaligned 16 state. Always fetch valid the cycle before.}
-coverage exclude -line 185 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never aligner_ready when entering misaligned 16 state. Always fetch valid the cycle before.}
 coverage exclude -line 460 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {We dont support OBI error.}
-coverage exclude -line 459 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {We dont support OBI error.}
 coverage exclude -line 549 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/alu_i -comment {Default part of uniqu_case for vector mode never reached.}
 coverage exclude -line 579 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/alu_i -comment {Default part of uniqu_case for vector mode never reached.}
 coverage exclude -line 608 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/alu_i -comment {Default part of uniqu_case for vector mode never reached.}
@@ -65,24 +55,18 @@ coverage exclude -line 90 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_
 coverage exclude -line 97 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {Fifo never empty when trying to push and pop at the same time.}
 coverage exclude -line 127 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {flush_but_first is dependent on !fifo_empty so this is unreachable.}
 coverage exclude -line 128 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {flush_but_first is dependent on !fifo_empty so this is unreachable.}
-coverage exclude -line 126 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {flush_but_first is dependent on !fifo_empty so this is unreachable.}
 coverage exclude -line 81 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {We never overflow the fifo.}
 coverage exclude -line 90 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {We never underflow the fifo.}
 coverage exclude -line 126 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {flush_but_first is dependent on !fifo_empty so this is unreachable.}
 coverage exclude -line 127 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {flush_but_first is dependent on !fifo_empty so this is unreachable.}
 coverage exclude -line 128 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {flush_but_first is dependent on !fifo_empty so this is unreachable.}
 coverage exclude -line 135 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {Case 2'b00 has been added for completion but is never used.}
-coverage exclude -line 203 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No cv.elw in this configuration.}
-coverage exclude -line 204 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No cv.elw in this configuration.}
-coverage exclude -line 321 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {Data error not used.}
-coverage exclude -line 322 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {Data error not used.}
-coverage exclude -line 397 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {We are in PULP_OBI == 0 configuration. In this configuration, trans_valid is always asserted when used in this expression.}
 coverage exclude -line 135 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {Case 2'b00 has been added for completion but is never used.}
 coverage exclude -line 155 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {2'b11 choice that never exists in the decoder.}
 coverage exclude -line 295 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {2'b11 choice that never exists in the decoder.}
-coverage exclude -line 2767 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreacheable code as cur_priv_lvl_i is at maximum value.}
-coverage exclude -line 2765 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreacheable code as cur_priv_lvl_i is at maximum value.}
-coverage exclude -line 2765 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreacheable code as cur_priv_lvl_i is at maximum value.}
+coverage exclude -line 2784 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreacheable code as cur_priv_lvl_i is at maximum value.}
+coverage exclude -line 2782 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreacheable code as cur_priv_lvl_i is at maximum value.}
+coverage exclude -line 2782 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreacheable code as cur_priv_lvl_i is at maximum value.}
 coverage exclude -line 419 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No Secure interrupt line. irq_sec_i tied to 0. }
 coverage exclude -line 451 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. }
 coverage exclude -line 452 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. }
@@ -138,8 +122,6 @@ coverage exclude -line 941 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb
 coverage exclude -line 1051 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Single-step not possible during debug mode.}
 coverage exclude -line 1062 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Single-step not possible during debug mode.}
 coverage exclude -line 1072 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Single-step not possible during debug mode.}
-coverage exclude -line 299 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.}
-coverage exclude -line 844 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No PC = Hwloop1 end & Hwloop 1 counter = 0 in DECODE_HWLOOP FSM state.}
 coverage exclude -line 418 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No Secure interrupt line. irq_sec_i tied to 0. }
 coverage exclude -line 421 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.}
 coverage exclude -line 447 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. }
@@ -177,5 +159,8 @@ coverage exclude -line 1131 -code b -item 2 -scope /uvmt_cv32e40p_tb/dut_wrap/cv
 coverage exclude -line 1230 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. }
 coverage exclude -line 1237 -code b -item 1 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. }
 coverage exclude -line 1237 -code b -item 2 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. }
+coverage exclude -line 399 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No interrupt during debug mode. To waive corner case to happen during FIRST_FETCH 1 clk cycle. }
+coverage exclude -line 640 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {HWLoop1 cannot be nested in HWLoop0.}
+coverage exclude -line 675 -code b -allfalse -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No case when ID not ready for single stepped instruction. }
 coverage exclude -code bcefs -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/interrupt_assert_i -recursive -comment {this is TB module bind to RTL. No need code coverage.}
 coverage exclude -code bcefs -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/prefetch_controller_i/prefetch_controller_sva -recursive -comment {this is TB module bind to RTL. No need code coverage.}