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CV32E40Pv2 Verification update #2357

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b02c745
Add fp testcases information into verif plan
dd-baoshan Oct 30, 2023
7da3501
add new interface for coverage used for cv32e40p specific floating po…
Nov 30, 2023
2ce11c8
add configs fpu_latency,rv32f_fcov_en,zfinx_fcov_en based on cv32e40p…
Nov 30, 2023
5bc131a
added cv32e40p specific floating instr specific coverage for rv32f an…
Nov 30, 2023
678d3d7
Merge pull request #95 from XavierAubert/cv32e40p/vja_fcov
dd-baoshan Nov 30, 2023
b581328
Enhance coverage to capture locations within hwloop for specific events
dd-baoshan Dec 1, 2023
cef23e5
Merge pull request #96 from XavierAubert/cv32e40p/bsm-Improve_hwloop_…
dd-baoshan Dec 1, 2023
ea125c3
Update multicycle latency
dd-baoshan Dec 1, 2023
4ccad4b
Update core-dv test for fp mstatus fs
dd-baoshan Dec 1, 2023
590d897
minor update
dd-baoshan Dec 1, 2023
9b02a13
Merge pull request #97 from XavierAubert/cv32e40p/bsm-fp_udpate_testc…
dd-baoshan Dec 1, 2023
03a57e1
F/Zfinx custom fcov update removing redundant cp, optimize crosses wi…
Dec 1, 2023
44647b9
Replace and rework COMMON_HWLOOP_EXC_HANDLING_CODE to make it more ge…
Dec 1, 2023
e444fa7
Re-enable ImperasDV isacov, keeping PULP coverage disabled temporarily
Dec 1, 2023
6754aeb
Update cv32e40p core hash
Dec 1, 2023
13f5a60
Resolve issue of avail_regs of riscv_rand_instr_stream not getting ra…
Dec 1, 2023
807d038
Merge pull request #98 from XavierAubert/cv32e40p/vja_ww48_fixes
Dec 1, 2023
2fba315
update randomize_avail_regs again to solve issues with compress instr…
Dec 2, 2023
add4b10
Merge pull request #99 from XavierAubert/cv32e40p/vja_corev_dv_fix
Dec 2, 2023
e559c79
Increase limit to fix regression issue
dd-baoshan Dec 4, 2023
213c6e2
Merge pull request #100 from XavierAubert/cv32e40p/bsm-fix_regr_issue…
dd-baoshan Dec 4, 2023
e8fef3e
Fix ucdb merge issue
dd-baoshan Dec 8, 2023
e30a396
Merge pull request #102 from XavierAubert/cv32e40p/bsm-Fix_ucdb_merge…
dd-baoshan Dec 8, 2023
3eeb856
add func store_instr_gpr_handling to use reserved reg from cfg for st…
Dec 12, 2023
664debd
add init for str instr's reserved source registers rs1/rs3 for debug …
Dec 12, 2023
89adbba
add override for gen_init_section to initialize str instr reserved re…
Dec 12, 2023
6d71cd7
add cv32e40p_instr_gen_config object for the class and remove all oth…
Dec 12, 2023
8bdfa16
remove workaround which was excluding pulp store instr in debug program
Dec 12, 2023
7ad565b
update cv32e40p core hash
Dec 12, 2023
3c4ffcf
Merge pull request #103 from XavierAubert/cv32e40p/vja_ww50_fixes
Dec 12, 2023
fbae748
temporarily remove cluster tests and build until cluster tb ready
Dec 12, 2023
8f50e97
move corev_rand_pulp_hwloop_exception_with_int_debug_trigger to long …
Dec 12, 2023
1fd49ef
update cv32e40p core hash
Dec 12, 2023
308f587
Merge pull request #104 from XavierAubert/cv32e40p/vja_regress
Dec 12, 2023
a58a0a2
Increased a bit Embench test compilation timeout.
Dec 12, 2023
b4558c5
Corrected Coremark compilation options and added context save/restore…
Dec 12, 2023
9f9f031
Inverted csr writes in floating point enable function to have a clean…
Dec 12, 2023
f428792
Better/global correction of debug assertion.
Dec 12, 2023
183d284
Merge pull request #105 from XavierAubert/cv32e40p/dev_dd_pgo
Dec 12, 2023
66521ba
Updated CORE hash.
Dec 12, 2023
d6403a9
Merge pull request #106 from XavierAubert/cv32e40p/dev_dd_pgo
Dec 12, 2023
2c533f5
Fix ucdb merge issue which related to rtl path references
dd-baoshan Dec 13, 2023
5b35e7f
Merge pull request #107 from XavierAubert/cv32e40p/bsm-fix_ucdb_merge…
dd-baoshan Dec 13, 2023
59d8bde
Fix hwloop cvg issue for mix events with irq
dd-baoshan Dec 13, 2023
a9d04e0
Merge pull request #108 from XavierAubert/cv32e40p/bsm-fix_hwloop_cov…
dd-baoshan Dec 13, 2023
e7c96e3
Added mstatus.fs write to initial state before fcsr clear.
Dec 13, 2023
da1a81a
Merge pull request #109 from XavierAubert/cv32e40p/dev_dd_pgo
Dec 13, 2023
08a6fee
Merge pull request #75 from XavierAubert/cv32e40p/bsm-fp_udpate_test_…
dd-baoshan Dec 13, 2023
5a761c6
Another fix for debug assertion (trigger match and branch).
Dec 14, 2023
7630a67
Merge pull request #110 from XavierAubert/cv32e40p/dev_dd_pgo
Dec 14, 2023
3dbad3a
remove coverpoint and crosses related to if_stage
Dec 15, 2023
b5d0b68
checked for coverage sampling excluded for debug mode and debug scena…
Dec 15, 2023
bd6630f
split hwloop instr for 0 and 1 and cv_sle cv_sleu update
Dec 15, 2023
1903163
replace instr wildcard bins with macros
Dec 15, 2023
7d79a6b
replace rvfi_insn with pipeline id_stage signal and chk debug_req cp …
Dec 15, 2023
4144152
update cp and cross naming, add trigger crosses and conditions
Dec 15, 2023
ea7751e
re-enable imperas isacov for pulp instr
Dec 15, 2023
4b5afb2
add debug signals for cov_if
Dec 15, 2023
ad0648e
fix cb inouts
Dec 15, 2023
36d1b29
add new test corev_rand_pulp_instr_debug and rand debug test_cfg
Dec 15, 2023
62cc412
Merge pull request #111 from XavierAubert/cv32e40p/vja_fcov_fixes
Dec 15, 2023
19e0b63
Fix hwloop cov model issue during debug entry due to cbreak. Fix hwlo…
dd-baoshan Dec 21, 2023
932bf97
Merge pull request #112 from XavierAubert/cv32e40p/bsm-fix_hwloop_cov…
dd-baoshan Dec 21, 2023
33f6f8c
Temporary workaround for GNU GCC issue #36 (https://github.com/openhw…
Dec 21, 2023
e47cbdb
Merge pull request #113 from XavierAubert/cv32e40p/dev_dd_pgo
Dec 21, 2023
6232a95
Merge pull request #114 from XavierAubert/cv32e40p/dev
dd-baoshan Dec 22, 2023
c0f098e
Added more options to run_many
Dec 22, 2023
0893ad7
Changed regression running options for debug_test_boot_set test
Dec 22, 2023
46c038d
Merge pull request #115 from XavierAubert/cv32e40p/dev_dd_pgo
Dec 22, 2023
9ed9aa2
Improve to handle different trap scenarioes
dd-baoshan Dec 26, 2023
fc50ee4
Merge pull request #116 from XavierAubert/cv32e40p/bsm-fix_hwloop_cov…
dd-baoshan Dec 26, 2023
7cafed8
fix issue for MAC instructions not getting has_rd set
Dec 26, 2023
46eee92
remove C_SWSP, C_FSWSP from randomize_debug_rom_instr to exclude from…
Dec 26, 2023
f288a44
fix issue due to no debug_exception handler causing debug progam gpr,…
Dec 26, 2023
bec5699
fix issue due to illegal instr inserted in hwloop body from sequence …
Dec 26, 2023
f932ccb
update cv32e40p core hash
Dec 26, 2023
d3ff477
add gen_limit_debug_req test cfg yaml and modify gen_rand_debug_req f…
Dec 26, 2023
b86ff58
add a new test for hwloop with random interrupts,trigger and ebreak
Dec 26, 2023
5c83ea1
add new tests for debug combinations with corev_rand_pulp_instr_debug…
Dec 26, 2023
fbac98a
Merge pull request #117 from XavierAubert/cv32e40p/vja_ww52_fixes
Dec 26, 2023
2cdadd5
corrected testname
Dec 26, 2023
68ca87d
Merge pull request #118 from XavierAubert/cv32e40p/vja_regress
Dec 26, 2023
b6ada05
Fix issue when exception happen within debug mode
dd-baoshan Dec 27, 2023
2bdfab7
Merge pull request #119 from XavierAubert/cv32e40p/bsm-fix_hwloop_cov…
dd-baoshan Dec 27, 2023
c5cdd27
add multiuserenv switch for vcover merge
dd-baoshan Dec 29, 2023
d4e38a5
Add tb params and cov bins macros for ISA instructions
dd-baoshan Dec 29, 2023
61b536f
allow hwloop cvg model need to handle exception within debug mode sce…
dd-baoshan Dec 29, 2023
36350b6
Merge pull request #120 from XavierAubert/cv32e40p/bsm-fix_hwloop_cvg…
dd-baoshan Dec 30, 2023
8fd9fc3
Fix regress due to previous fixes
dd-baoshan Jan 2, 2024
90792c6
Merge pull request #122 from XavierAubert/cv32e40p/bsm-fix_hwloop_cov…
dd-baoshan Jan 2, 2024
15ca4cc
Add illegal Instr contraint for RV32FC
dd-baoshan Jan 3, 2024
4cc518f
Merge pull request #123 from XavierAubert/cv32e40p/bsm-fix_regr_issue…
dd-baoshan Jan 3, 2024
6c6851f
Enable define for some extended Imperas ISA coverpoints
dd-baoshan Jan 9, 2024
477c3c1
modify msg for rerun command
dd-baoshan Jan 9, 2024
a05e015
Fix corner case issues found in random seed
dd-baoshan Jan 9, 2024
05d8227
Add random fpu streams with interrupt and debug events
dd-baoshan Jan 9, 2024
8df2144
Merge pull request #124 from XavierAubert/cv32e40p/bsm-update_tb_file…
dd-baoshan Jan 9, 2024
e81e508
Disable trace logs generations in regression using vrun
dd-baoshan Jan 10, 2024
dc81457
Merge pull request #125 from XavierAubert/cv32e40p/bsm-disable_logs_i…
dd-baoshan Jan 10, 2024
2f5ac42
Modify code coverage collection types
dd-baoshan Jan 10, 2024
069dc31
Use reduced debug req in these tests
dd-baoshan Jan 10, 2024
969eee4
Merge pull request #126 from XavierAubert/cv32e40p/bsm-update_tb_file…
dd-baoshan Jan 10, 2024
4f442d0
added seed field option in regress YAML files to specify a unique see…
XavierAubert Jan 11, 2024
d223e87
updated failing debug_test_boot_set test item in regress files
XavierAubert Jan 11, 2024
c240e07
Merge pull request #127 from XavierAubert/cv32e40p/xau_fix
dd-baoshan Jan 12, 2024
ee0a2c2
Increase timeout
dd-baoshan Jan 12, 2024
6e7ff88
Tempoary exclude Imperas func coverage. Re-enable when newer version …
dd-baoshan Jan 12, 2024
19edee3
Fix to handle corner case events
dd-baoshan Jan 12, 2024
4fe525d
Merge pull request #128 from XavierAubert/cv32e40p/bsm-update_tb_file…
dd-baoshan Jan 12, 2024
76f9593
Added FP enable depending on configuration.
Jan 15, 2024
7716d48
Indentation corrected.
Jan 15, 2024
621478f
Merge pull request #129 from XavierAubert/cv32e40p/dev_dd_pgo
Jan 15, 2024
93117b0
Increase test timeout
dd-baoshan Jan 19, 2024
d3e7cad
Fix to handle case when irq, debug and exception happen together
dd-baoshan Jan 19, 2024
5f3881f
Update core-v-cores hash to head
dd-baoshan Jan 19, 2024
3de68c7
Update fp debug test to reserved debug pointer register
dd-baoshan Jan 19, 2024
fa20985
Merge pull request #130 from XavierAubert/cv32e40p/bsm-update_tb_file…
dd-baoshan Jan 19, 2024
2929c3f
added directed test for all illegal instruction for custom opcodes
XavierAubert Jan 19, 2024
04b9d38
fixed typo in filename
XavierAubert Jan 19, 2024
21c5419
added custom opcodes test to the pulp regression list
XavierAubert Jan 19, 2024
1e6cc55
Merge pull request #131 from XavierAubert/cv32e40p/illegal_instr_test_v2
XavierAubert Jan 19, 2024
01c1201
added missings cases inside custom-3 opcodes (cv.sub)
XavierAubert Jan 22, 2024
56ba26f
Prevent post increment store from corrupting the main code
dd-baoshan Jan 23, 2024
d76e6b6
To prevent compress store sp from corrupting the main code
dd-baoshan Jan 23, 2024
929164e
Improve simtime by reducing hwloop counts; Add directed class for lar…
dd-baoshan Jan 25, 2024
87d4b0c
Edit and Add cover points for cp_lpcount
dd-baoshan Jan 25, 2024
4361141
Add hwloop directed tests and regression yaml files
dd-baoshan Jan 25, 2024
c4be393
Merge pull request #132 from XavierAubert/cv32e40p/bsm-update_tb_file…
dd-baoshan Jan 25, 2024
69c1e7e
Merge pull request #133 from XavierAubert/cv32e40p/dev
dd-baoshan Jan 25, 2024
a111661
Increase debug rom space
dd-baoshan Jan 26, 2024
e266d70
Merge pull request #134 from XavierAubert/cv32e40p/bsm-update_tb_file…
dd-baoshan Jan 26, 2024
105c346
Merge pull request #135 from XavierAubert/cv32e40p/illegal_instr_test_v2
XavierAubert Jan 26, 2024
e1a8ab4
added 3 instructions that are not with OP=custom
XavierAubert Jan 26, 2024
acccf23
Merge pull request #136 from XavierAubert/cv32e40p/illegal_instr_test_v2
XavierAubert Jan 26, 2024
befb435
Revert previous changes
dd-baoshan Jan 27, 2024
990dcb6
Merge pull request #137 from XavierAubert/cv32e40p/bsm-update_tb_file…
dd-baoshan Jan 27, 2024
7fcc2e5
Fix to handle corner case events - valid exception trap following by …
dd-baoshan Jan 29, 2024
a290dbc
Merge pull request #138 from XavierAubert/cv32e40p/bsm-update_tb_file…
dd-baoshan Jan 29, 2024
8206574
simplified specific seed handling as requested
XavierAubert Feb 2, 2024
4cc613a
Merge pull request #142 from XavierAubert/cv32e40p/xau_fix
XavierAubert Feb 2, 2024
98ba636
added header
XavierAubert Feb 2, 2024
940f014
Merge pull request #143 from XavierAubert/cv32e40p/illegal_instr_test_v2
XavierAubert Feb 2, 2024
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1 change: 1 addition & 0 deletions bin/run_embench.py
Original file line number Diff line number Diff line change
Expand Up @@ -190,6 +190,7 @@ def main():
f'--ldflags=-T{paths["bsp"]}/link.ld',
f'--builddir={args.builddir}',
f'--logdir={args.logdir}',
f'--timeout=15',
'--clean']
logger.info(f"Calling build script: {' '.join(cmd)}")
try:
Expand Down
32 changes: 23 additions & 9 deletions bin/run_many
Original file line number Diff line number Diff line change
Expand Up @@ -7,34 +7,48 @@
# Uses a different seed for each run.
# Generates the same "make test" command generated by the "ci_check" script.
#
# Usage: run_many [test-program] [simulator] [nruns]
# For example, "run_many hello-world vcs 2" will run the hello-world
# Usage: run_many [cfg] [test-program] [simulator] [nruns] [user_flags]
# For example, "run_many default hello-world vcs 2" will run the hello-world
# test-program with VCS twice.
#
# TODO: command-line argument processing is primitive.

if [ $# -gt 0 ]
then
TESTPROGRAM=$1
CFG=$1
else
TESTPROGRAM=hello-world
CFG=default
fi

if [ $# -gt 1 ]
then
SIM=$2
TESTPROGRAM=$2
else
SIM=vcs
TESTPROGRAM=hello-world
fi

if [ $# -gt 2 ]
then
RUNS=$3
SIM=$3
else
SIM=vcs
fi

if [ $# -gt 3 ]
then
RUNS=$4
else
RUNS=2
fi
let RUNSM1=$RUNS-1

if [ $# -gt 4 ]
then
USER_FLAGS=$5
else
USER_FLAGS=
fi

if [[ -z "${CV_CORE}" ]];
then
echo CV_CORE not defined... cannot proceed.
Expand All @@ -56,8 +70,8 @@ counter=0
until [ $counter -gt $RUNSM1 ]
do
THISSEED=`date +%N`
echo "make test SEED=$THISSEED TEST=$TESTPROGRAM SIMULATOR=$SIM GEN_START_INDEX=$counter RUN_INDEX=$counter USE_ISS=NO"
make test SEED=$THISSEED TEST=$TESTPROGRAM SIMULATOR=$SIM GEN_START_INDEX=$counter RUN_INDEX=$counter USE_ISS=NO
echo "make test CFG=$CFG TEST=$TESTPROGRAM SIMULATOR=$SIM GEN_START_INDEX=$counter RUN_INDEX=$counter USE_ISS=NO SEED=$THISSEED VSIM_USER_FLAGS=$USER_FLAGS"
make test CFG=$CFG TEST=$TESTPROGRAM SIMULATOR=$SIM GEN_START_INDEX=$counter RUN_INDEX=$counter USE_ISS=NO SEED=$THISSEED VSIM_USER_FLAGS=$USER_FLAGS
((counter++))
done

Expand Down
15 changes: 10 additions & 5 deletions bin/templates/regress_rmdb.j2
Original file line number Diff line number Diff line change
Expand Up @@ -61,7 +61,10 @@
</usertcl>

<usertcl name="seedGen">
proc getSeeds { num mode regr_name } {
proc getSeeds { num mode regr_name seed_value } {
if { $seed_value != "" } {
return $seed_value
}
if {[string equal $mode "FIXED"]} {
return [GetRandomValues $num]
}
Expand Down Expand Up @@ -141,6 +144,7 @@


<!-- =========== Builds =========== START -->
<!-- Note: ENABLE_TRACE_LOG=NO is removed from print msg as rerun is require tracer to be enable -->
{% for build in r.get_builds() %}
<runnable name="{{r.name}}_{{build.name}}" type="group" sequential="no">
<!-- set of parameters to be given to leaf runnables -->
Expand All @@ -158,8 +162,8 @@
{% endfor %}
</members>
<preScript launch="exec">
<command> echo "BUILD RUNCMD: {{build.cmd}} CV_CORE={{project}} CFG={{build.cfg}} {{toolchain|upper}}=1 SIMULATOR={{build.simulator}} USE_ISS={{regress_macros.yesorno(build.iss)}} COV={{regress_macros.yesorno(build.cov)}} {{regress_macros.cv_results(results_path)}} {{makeargs}}"</command>
<command> cd {{build.abs_dir}} &amp;&amp; {{build.cmd}} CV_CORE={{project}} CFG={{build.cfg}} {{toolchain|upper}}=1 SIMULATOR={{build.simulator}} USE_ISS={{regress_macros.yesorno(build.iss)}} COV={{regress_macros.yesorno(build.cov)}} {{regress_macros.cv_results(results_path)}} {{makeargs}} </command>
<command> echo "BUILD RUNCMD: {{build.cmd}} CV_CORE={{project}} CFG={{build.cfg}} {{toolchain|upper}}=1 SIMULATOR={{build.simulator}} ENABLE_TRACE_LOG=NO USE_ISS={{regress_macros.yesorno(build.iss)}} COV={{regress_macros.yesorno(build.cov)}} {{regress_macros.cv_results(results_path)}} {{makeargs}}"</command>
<command> cd {{build.abs_dir}} &amp;&amp; {{build.cmd}} CV_CORE={{project}} CFG={{build.cfg}} {{toolchain|upper}}=1 SIMULATOR={{build.simulator}} ENABLE_TRACE_LOG=NO USE_ISS={{regress_macros.yesorno(build.iss)}} COV={{regress_macros.yesorno(build.cov)}} {{regress_macros.cv_results(results_path)}} {{makeargs}} </command>
</preScript>
</runnable>
{% endfor %}
Expand All @@ -182,7 +186,7 @@
<parameter name="t_test_cfg_name" type="tcl">[getTestCfgName "(%t_test_cfg:%)"]</parameter>
<parameter name="t_iss" type="tcl">[getParameterByPriorityYesOrNo "{{iss}}" "{{t.iss}}" "(%build_iss:%)"]</parameter>
<parameter name="t_cov" type="tcl">[getParameterByPriorityYesOrNo "{{coverage}}" "{{t.cov}}" "(%build_cov:%)"]</parameter>
<parameter name="seeds" type="tcl">[getSeeds "{{t.num}}" "(%SEED_MODE:RAND%)" "(%reg_name%)"]</parameter>
<parameter name="seeds" type="tcl">[getSeeds "{{t.num}}" "(%SEED_MODE:RAND%)" "(%reg_name%)" "{{t.seed}}"]</parameter>
<parameter name="ucdb_path" type="tcl">[file join "(%results_sim_path%)" "(%t_cfg%)" "{{t.testname}}" "(%t_test_cfg_name:%)" (%t_iteration%)]</parameter>
<parameter name="testname" type="tcl">[getTestName "{{t.testname}}" "(%t_cfg%)" "(%t_test_cfg_name:%)" (%t_iteration%)]</parameter>
<parameter name="ucdb_basename" type="tcl">[getUCDBFilename "{{t.testname}}" "(%t_test_cfg_name:%)"]</parameter>
Expand All @@ -199,14 +203,15 @@

{% endfor %}

<!-- Note: COMP=0 is removed form print msg as rerun is require recompile all the time-->
<runnable name="simulation" type="task">
{% if lsf != None %}
<method name="grid" gridtype="lsf" action="execScript">
<command> {{lsf}} -P {{project}} -J (%RUNNABLE%) (%WRAPPER%) </command>
</method>
{% endif %}
<execScript launch="exec" usestderr="no">
<command> echo " TEST RUNCMD: (%t_cmd%) CHECK_SIM_RESULT={{regress_macros.yesorno(check_sim_results)}} COMP=0 CV_CORE={{project}} {{toolchain|upper}}=1 CFG=(%t_cfg%) TEST_CFG_FILE=(%t_test_cfg:%) SIMULATOR=(%t_simulator%) USE_ISS=(%t_iss:%) COV=(%t_cov:%) RUN_INDEX=(%t_iteration%) GEN_START_INDEX=(%t_iteration%) SEED=(%t_iteration%) {{regress_macros.cv_results(results_path)}} {{makeargs}} (%t_makearg%)"</command>
<command> echo " TEST RUNCMD: (%t_cmd%) CHECK_SIM_RESULT={{regress_macros.yesorno(check_sim_results)}} CV_CORE={{project}} {{toolchain|upper}}=1 CFG=(%t_cfg%) TEST_CFG_FILE=(%t_test_cfg:%) SIMULATOR=(%t_simulator%) USE_ISS=(%t_iss:%) COV=(%t_cov:%) RUN_INDEX=(%t_iteration%) GEN_START_INDEX=(%t_iteration%) SEED=(%t_iteration%) {{regress_macros.cv_results(results_path)}} {{makeargs}} (%t_makearg%)"</command>
<command> echo " logfile: (%log_file%)"</command>
<command> echo " RTL repo: CV_CORE_REPO : ${CV_CORE_REPO}"</command>
<command> echo " CV_CORE_BRANCH: ${CV_CORE_BRANCH}"</command>
Expand Down
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4 changes: 2 additions & 2 deletions cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr.sv
Original file line number Diff line number Diff line change
Expand Up @@ -230,7 +230,7 @@ class cv32e40p_instr extends riscv_instr;
// special overrides for xcorev

// for ALU, there exists variations for R and S types
if (category == ALU) begin
if (category inside {ALU,MAC}) begin
if (instr_name inside {CV_CLIP, CV_CLIPU}) has_imm = 1'b1;
if (format == S_FORMAT) has_rd = 1'b1;
end
Expand Down Expand Up @@ -698,7 +698,7 @@ class cv32e40p_instr extends riscv_instr;
imm_str = $sformatf("%0d", $signed(imm[5:0]));
end
end else
super.update_imm_str();
super.update_imm_str();
endfunction

// `include "isa/riscv_instr_cov.svh"
Expand Down
1 change: 1 addition & 0 deletions cv32e40p/env/corev-dv/custom/riscv_instr_gen_config.sv
Original file line number Diff line number Diff line change
Expand Up @@ -415,6 +415,7 @@ class riscv_instr_gen_config extends uvm_object;
if (fix_sp) {
sp == SP;
}
sp dist {SP := 15, [TP:T6] := 1}; // higher change assign to reg x2
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sp != tp;
!(sp inside {GP, RA, ZERO});
!(tp inside {GP, RA, ZERO});
Expand Down
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