CV32E40Pv2 Verification update

bin/lib/cv_regression.py

@@ -96,6 +96,11 @@ def __init__(self, **kwargs):
         if not hasattr(self, 'log'):
             self.log = self.name
 
+        if hasattr(self, 'seed'):
+            self.seed_override = 1
+        else:
+            self.seed_override = 0
+
     def set_cov(self):
         '''Set the coverage flag based on app setting.
         If cov already defined (from testlist), then ignore'''

bin/run_embench.py

@@ -190,6 +190,7 @@ def main():
          f'--ldflags=-T{paths["bsp"]}/link.ld',
          f'--builddir={args.builddir}',
          f'--logdir={args.logdir}',
+         f'--timeout=15',
          '--clean']
   logger.info(f"Calling build script: {' '.join(cmd)}")
   try:

bin/run_many

@@ -7,34 +7,48 @@
 # Uses a different seed for each run.
 # Generates the same "make test" command generated by the "ci_check" script.
 #
-# Usage:   run_many [test-program] [simulator] [nruns]
-#          For example, "run_many hello-world vcs 2" will run the hello-world
+# Usage:   run_many [cfg] [test-program] [simulator] [nruns] [user_flags]
+#          For example, "run_many default hello-world vcs 2" will run the hello-world
 #          test-program with VCS twice.
 #
 # TODO:    command-line argument processing is primitive.
 
 if [ $# -gt 0 ]
 then
-  TESTPROGRAM=$1
+  CFG=$1
 else
-  TESTPROGRAM=hello-world
+  CFG=default
 fi
 
 if [ $# -gt 1 ]
 then
-  SIM=$2
+  TESTPROGRAM=$2
 else
-  SIM=vcs
+  TESTPROGRAM=hello-world
 fi
 
 if [ $# -gt 2 ]
 then
-  RUNS=$3
+  SIM=$3
+else
+  SIM=vcs
+fi
+
+if [ $# -gt 3 ]
+then
+  RUNS=$4
 else
   RUNS=2
 fi
 let RUNSM1=$RUNS-1
 
+if [ $# -gt 4 ]
+then
+  USER_FLAGS=$5
+else
+  USER_FLAGS=
+fi
+
 if [[ -z "${CV_CORE}" ]];
 then
   echo CV_CORE not defined... cannot proceed.
@@ -56,8 +70,8 @@ counter=0
 until [ $counter -gt $RUNSM1 ]
 do
   THISSEED=`date +%N`
-  echo "make test SEED=$THISSEED TEST=$TESTPROGRAM SIMULATOR=$SIM GEN_START_INDEX=$counter RUN_INDEX=$counter USE_ISS=NO"
-  make test SEED=$THISSEED TEST=$TESTPROGRAM SIMULATOR=$SIM GEN_START_INDEX=$counter RUN_INDEX=$counter USE_ISS=NO
+  echo "make test CFG=$CFG TEST=$TESTPROGRAM SIMULATOR=$SIM GEN_START_INDEX=$counter RUN_INDEX=$counter USE_ISS=NO SEED=$THISSEED VSIM_USER_FLAGS=$USER_FLAGS"
+  make test CFG=$CFG TEST=$TESTPROGRAM SIMULATOR=$SIM GEN_START_INDEX=$counter RUN_INDEX=$counter USE_ISS=NO SEED=$THISSEED VSIM_USER_FLAGS=$USER_FLAGS
   ((counter++))
 done
 

bin/templates/regress_rmdb.j2

@@ -61,7 +61,10 @@
     </usertcl>
 
     <usertcl name="seedGen">
-        proc getSeeds { num mode regr_name } {
+        proc getSeeds { num mode regr_name seed_override seed_value } {
+            if { $seed_override == "1" } {
+                return $seed_value
+            }
             if {[string equal $mode "FIXED"]} {
                 return [GetRandomValues $num]
             }
@@ -141,6 +144,7 @@
 
 
     <!-- =========== Builds =========== START -->
+            <!-- Note: ENABLE_TRACE_LOG=NO is removed from print msg as rerun is require tracer to be enable -->
 {% for build in r.get_builds() %}
         <runnable name="{{r.name}}_{{build.name}}" type="group" sequential="no">
             <!-- set of parameters to be given to leaf runnables -->
@@ -158,8 +162,8 @@
 {% endfor %}
             </members>
             <preScript launch="exec">
-                <command> echo "BUILD RUNCMD: {{build.cmd}} CV_CORE={{project}} CFG={{build.cfg}} {{toolchain|upper}}=1 SIMULATOR={{build.simulator}} USE_ISS={{regress_macros.yesorno(build.iss)}} COV={{regress_macros.yesorno(build.cov)}} {{regress_macros.cv_results(results_path)}} {{makeargs}}"</command>
-                <command> cd {{build.abs_dir}} &amp;&amp; {{build.cmd}} CV_CORE={{project}} CFG={{build.cfg}} {{toolchain|upper}}=1 SIMULATOR={{build.simulator}} USE_ISS={{regress_macros.yesorno(build.iss)}} COV={{regress_macros.yesorno(build.cov)}} {{regress_macros.cv_results(results_path)}} {{makeargs}} </command>
+                <command> echo "BUILD RUNCMD: {{build.cmd}} CV_CORE={{project}} CFG={{build.cfg}} {{toolchain|upper}}=1 SIMULATOR={{build.simulator}} ENABLE_TRACE_LOG=NO USE_ISS={{regress_macros.yesorno(build.iss)}} COV={{regress_macros.yesorno(build.cov)}} {{regress_macros.cv_results(results_path)}} {{makeargs}}"</command>
+                <command> cd {{build.abs_dir}} &amp;&amp; {{build.cmd}} CV_CORE={{project}} CFG={{build.cfg}} {{toolchain|upper}}=1 SIMULATOR={{build.simulator}} ENABLE_TRACE_LOG=NO USE_ISS={{regress_macros.yesorno(build.iss)}} COV={{regress_macros.yesorno(build.cov)}} {{regress_macros.cv_results(results_path)}} {{makeargs}} </command>
             </preScript>
         </runnable>
 {% endfor %}
@@ -182,7 +186,7 @@
                     <parameter name="t_test_cfg_name" type="tcl">[getTestCfgName "(%t_test_cfg:%)"]</parameter>
                     <parameter name="t_iss"           type="tcl">[getParameterByPriorityYesOrNo "{{iss}}" "{{t.iss}}" "(%build_iss:%)"]</parameter>
                     <parameter name="t_cov"           type="tcl">[getParameterByPriorityYesOrNo "{{coverage}}" "{{t.cov}}" "(%build_cov:%)"]</parameter>
-                    <parameter name="seeds"           type="tcl">[getSeeds "{{t.num}}" "(%SEED_MODE:RAND%)" "(%reg_name%)"]</parameter>
+                    <parameter name="seeds"           type="tcl">[getSeeds "{{t.num}}" "(%SEED_MODE:RAND%)" "(%reg_name%)" "{{t.seed_override}}" "{{t.seed}}"]</parameter>
                     <parameter name="ucdb_path"       type="tcl">[file join "(%results_sim_path%)" "(%t_cfg%)" "{{t.testname}}" "(%t_test_cfg_name:%)" (%t_iteration%)]</parameter>
                     <parameter name="testname"        type="tcl">[getTestName "{{t.testname}}" "(%t_cfg%)" "(%t_test_cfg_name:%)" (%t_iteration%)]</parameter>
                     <parameter name="ucdb_basename"   type="tcl">[getUCDBFilename "{{t.testname}}" "(%t_test_cfg_name:%)"]</parameter>
@@ -199,14 +203,15 @@
 
 {% endfor %}
 
+            <!-- Note: COMP=0 is removed form print msg as rerun is require recompile all the time-->
             <runnable name="simulation" type="task">
 {% if lsf != None %}
                 <method name="grid" gridtype="lsf" action="execScript">
                     <command> {{lsf}} -P {{project}} -J (%RUNNABLE%) (%WRAPPER%) </command>
                 </method>
 {% endif %}
                 <execScript launch="exec" usestderr="no">
-                    <command> echo " TEST RUNCMD: (%t_cmd%) CHECK_SIM_RESULT={{regress_macros.yesorno(check_sim_results)}} COMP=0 CV_CORE={{project}} {{toolchain|upper}}=1 CFG=(%t_cfg%) TEST_CFG_FILE=(%t_test_cfg:%) SIMULATOR=(%t_simulator%) USE_ISS=(%t_iss:%) COV=(%t_cov:%) RUN_INDEX=(%t_iteration%) GEN_START_INDEX=(%t_iteration%) SEED=(%t_iteration%) {{regress_macros.cv_results(results_path)}} {{makeargs}} (%t_makearg%)"</command>
+                    <command> echo " TEST RUNCMD: (%t_cmd%) CHECK_SIM_RESULT={{regress_macros.yesorno(check_sim_results)}} CV_CORE={{project}} {{toolchain|upper}}=1 CFG=(%t_cfg%) TEST_CFG_FILE=(%t_test_cfg:%) SIMULATOR=(%t_simulator%) USE_ISS=(%t_iss:%) COV=(%t_cov:%) RUN_INDEX=(%t_iteration%) GEN_START_INDEX=(%t_iteration%) SEED=(%t_iteration%) {{regress_macros.cv_results(results_path)}} {{makeargs}} (%t_makearg%)"</command>
                     <command> echo "     logfile: (%log_file%)"</command>
                     <command> echo "     RTL repo: CV_CORE_REPO  : ${CV_CORE_REPO}"</command>
                     <command> echo "               CV_CORE_BRANCH: ${CV_CORE_BRANCH}"</command>

cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr.sv

@@ -230,7 +230,7 @@ class cv32e40p_instr extends riscv_instr;
     // special overrides for xcorev
 
     // for ALU, there exists variations for R and S types
-    if (category == ALU) begin
+    if (category inside {ALU,MAC}) begin
       if (instr_name inside {CV_CLIP, CV_CLIPU}) has_imm = 1'b1;
       if (format == S_FORMAT) has_rd = 1'b1;
     end
@@ -698,7 +698,7 @@ class cv32e40p_instr extends riscv_instr;
         imm_str = $sformatf("%0d", $signed(imm[5:0]));
       end
     end else
-    super.update_imm_str();
+      super.update_imm_str();
   endfunction
 
   // `include "isa/riscv_instr_cov.svh"

cv32e40p/env/corev-dv/custom/riscv_instr_gen_config.sv

@@ -415,6 +415,7 @@ class riscv_instr_gen_config extends uvm_object;
     if (fix_sp) {
       sp == SP;
     }
+    sp dist {SP := 15, [TP:T6] := 1}; // higher change assign to reg x2
     sp != tp;
     !(sp inside {GP, RA, ZERO});
     !(tp inside {GP, RA, ZERO});