Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Fix debug module parameterization #1382

Merged
merged 3 commits into from
Sep 13, 2023
Merged

Fix debug module parameterization #1382

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
dd4b192
Re-factor halt and exception address as parameter
zarubaf Sep 11, 2023
1c3bde4
Add `HaltAddress` and `ExceptionAddress` to all configs
zarubaf Sep 13, 2023
272d417
Fix HaltAddress
zarubaf Sep 13, 2023
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
5 changes: 0 additions & 5 deletions Bender.yml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,6 @@ sources:
files:
- core/include/cv64a6_imafdcv_sv39_config_pkg.sv
- core/include/riscv_pkg.sv
- core/include/ariane_dm_pkg.sv
- core/include/ariane_pkg.sv
- core/mmu_sv39/tlb.sv
- core/mmu_sv39/mmu.sv
Expand All @@ -36,7 +35,6 @@ sources:
files:
- core/include/cv64a6_imafdc_sv39_config_pkg.sv
- core/include/riscv_pkg.sv
- core/include/ariane_dm_pkg.sv
- core/include/ariane_pkg.sv
- core/mmu_sv39/tlb.sv
- core/mmu_sv39/mmu.sv
Expand All @@ -47,7 +45,6 @@ sources:
files:
- core/include/cv32a6_imac_sv0_config_pkg.sv
- core/include/riscv_pkg.sv
- core/include/ariane_dm_pkg.sv
- core/include/ariane_pkg.sv
- core/mmu_sv32/cva6_tlb_sv32.sv
- core/mmu_sv32/cva6_mmu_sv32.sv
Expand All @@ -58,7 +55,6 @@ sources:
files:
- core/include/cv32a6_imac_sv32_config_pkg.sv
- core/include/riscv_pkg.sv
- core/include/ariane_dm_pkg.sv
- core/include/ariane_pkg.sv
- core/mmu_sv32/cva6_tlb_sv32.sv
- core/mmu_sv32/cva6_mmu_sv32.sv
Expand All @@ -69,7 +65,6 @@ sources:
files:
- core/include/cv32a6_imafc_sv32_config_pkg.sv
- core/include/riscv_pkg.sv
- core/include/ariane_dm_pkg.sv
- core/include/ariane_pkg.sv
- core/mmu_sv32/cva6_tlb_sv32.sv
- core/mmu_sv32/cva6_mmu_sv32.sv
Expand Down
1 change: 0 additions & 1 deletion Flist.ariane
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,6 @@
core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
core/include/riscv_pkg.sv
corev_apu/riscv-dbg/src/dm_pkg.sv
core/include/ariane_dm_pkg.sv
vendor/openhwgroup/cvfpu/src/fpnew_pkg.sv
core/include/ariane_pkg.sv
core/include/acc_pkg.sv
Expand Down
1 change: 0 additions & 1 deletion core/Flist.cva6
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -58,7 +58,6 @@ ${CVA6_REPO_DIR}/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mv
${CVA6_REPO_DIR}/core/include/config_pkg.sv
${CVA6_REPO_DIR}/core/include/${TARGET_CFG}_config_pkg.sv
${CVA6_REPO_DIR}/core/include/riscv_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_dm_pkg.sv
// Note: depends on fpnew_pkg, above
${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/axi/src/axi_pkg.sv
Expand Down
1 change: 0 additions & 1 deletion core/Flist.cva6_gate
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,6 @@
${CVA6_REPO_DIR}/core/include/config_pkg.sv
${CVA6_REPO_DIR}/core/include/${TARGET_CFG}_config_pkg.sv
${CVA6_REPO_DIR}/core/include/riscv_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_dm_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/axi/src/axi_pkg.sv

Expand Down
8 changes: 4 additions & 4 deletions core/csr_regfile.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1037,7 +1037,7 @@ module csr_regfile import ariane_pkg::*; #(
endcase
// save PC of next this instruction e.g.: the next one to be executed
dpc_d = {{riscv::XLEN-riscv::VLEN{pc_i[riscv::VLEN-1]}},pc_i};
dcsr_d.cause = ariane_dm_pkg::CauseBreakpoint;
dcsr_d.cause = ariane_pkg::CauseBreakpoint;
end

// we've got a debug request
Expand All @@ -1050,7 +1050,7 @@ module csr_regfile import ariane_pkg::*; #(
// jump to the base address
set_debug_pc_o = 1'b1;
// save the cause as external debug request
dcsr_d.cause = ariane_dm_pkg::CauseRequest;
dcsr_d.cause = ariane_pkg::CauseRequest;
end

// single step enable and we just retired an instruction
Expand All @@ -1072,7 +1072,7 @@ module csr_regfile import ariane_pkg::*; #(
end
debug_mode_d = 1'b1;
set_debug_pc_o = 1'b1;
dcsr_d.cause = ariane_dm_pkg::CauseSingleStep;
dcsr_d.cause = ariane_pkg::CauseSingleStep;
end
end
// go in halt-state again when we encounter an exception
Expand Down Expand Up @@ -1269,7 +1269,7 @@ module csr_regfile import ariane_pkg::*; #(

// if we are in debug mode jump to a specific address
if (debug_mode_q) begin
trap_vector_base_o = DmBaseAddress[riscv::VLEN-1:0] + ariane_dm_pkg::ExceptionAddress[riscv::VLEN-1:0];
trap_vector_base_o = DmBaseAddress[riscv::VLEN-1:0] + CVA6Cfg.ExceptionAddress[riscv::VLEN-1:0];
end

// check if we are in vectored mode, if yes then do BASE + 4 * cause we
Expand Down
4 changes: 3 additions & 1 deletion core/cva6.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -190,7 +190,9 @@ module cva6 import ariane_pkg::*; #(
bit'(XF8Vec),
unsigned'(NrRgprPorts),
unsigned'(NrWbPorts),
bit'(EnableAccelerator)
bit'(EnableAccelerator),
CVA6Cfg.HaltAddress,
CVA6Cfg.ExceptionAddress
};


Expand Down
2 changes: 1 addition & 1 deletion core/frontend/frontend.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -354,7 +354,7 @@ module frontend import ariane_pkg::*; #(
end
// 7. Debug
// enter debug on a hard-coded base-address
if (set_debug_pc_i) npc_d = ArianeCfg.DmBaseAddress[riscv::VLEN-1:0] + ariane_dm_pkg::HaltAddress[riscv::VLEN-1:0];
if (set_debug_pc_i) npc_d = ArianeCfg.DmBaseAddress[riscv::VLEN-1:0] + CVA6Cfg.HaltAddress[riscv::VLEN-1:0];
icache_dreq_o.vaddr = fetch_address;
end

Expand Down
48 changes: 0 additions & 48 deletions core/include/ariane_dm_pkg.sv
View file
Open in desktop

This file was deleted.

26 changes: 23 additions & 3 deletions core/include/ariane_pkg.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -166,13 +166,33 @@ package ariane_pkg;
localparam NR_RGPR_PORTS = 2;

// static debug hartinfo
localparam ariane_dm_pkg::hartinfo_t DebugHartInfo = '{
// debug causes
localparam logic [2:0] CauseBreakpoint = 3'h1;
localparam logic [2:0] CauseTrigger = 3'h2;
localparam logic [2:0] CauseRequest = 3'h3;
localparam logic [2:0] CauseSingleStep = 3'h4;
// amount of data count registers implemented
localparam logic [3:0] DataCount = 4'h2;

// address where data0-15 is shadowed or if shadowed in a CSR
// address of the first CSR used for shadowing the data
localparam logic [11:0] DataAddr = 12'h380; // we are aligned with Rocket here
typedef struct packed {
logic [31:24] zero1;
logic [23:20] nscratch;
logic [19:17] zero0;
logic dataaccess;
logic [15:12] datasize;
logic [11:0] dataaddr;
} hartinfo_t;

localparam hartinfo_t DebugHartInfo = '{
zero1: '0,
nscratch: 2, // Debug module needs at least two scratch regs
zero0: '0,
dataaccess: 1'b1, // data registers are memory mapped in the debugger
datasize: ariane_dm_pkg::DataCount,
dataaddr: ariane_dm_pkg::DataAddr
datasize: DataCount,
dataaddr: DataAddr
};

// enables a commit log which matches spikes commit log format for easier trace comparison
Expand Down
12 changes: 10 additions & 2 deletions core/include/config_pkg.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -44,6 +44,10 @@ package config_pkg;
int unsigned NrRgprPorts;
int unsigned NrWbPorts;
bit EnableAccelerator;
// Debug Module
// address to which a hart should jump when it was requested to halt
logic [63:0] HaltAddress;
logic [63:0] ExceptionAddress;
} cva6_cfg_t;

localparam cva6_cfg_t cva6_cfg_default = {
Expand Down Expand Up @@ -74,7 +78,9 @@ package config_pkg;
bit'(0), // XF8Vec
unsigned'(0), // NrRgprPorts
unsigned'(0), // NrWbPorts
bit'(0) // EnableAccelerator
bit'(0), // EnableAccelerator
64'h800, // HaltAddress
64'h808 // ExceptionAddress
} ;

localparam cva6_cfg_t cva6_cfg_empty = {
Expand Down Expand Up @@ -105,7 +111,9 @@ package config_pkg;
bit'(0), // XF8Vec
unsigned'(0), // NrRgprPorts
unsigned'(0), // NrWbPorts
bit'(0) // EnableAccelerator
bit'(0), // EnableAccelerator
64'h0, // HaltAddress
64'h0 // ExceptionAddress
} ;


Expand Down
4 changes: 3 additions & 1 deletion core/include/cv32a60x_config_pkg.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -103,7 +103,9 @@ package cva6_config_pkg;
bit'(0), // XF8Vec
unsigned'(0), // NrRgprPorts
unsigned'(0), // NrWbPorts
bit'(0) // EnableAccelerator
bit'(0), // EnableAccelerator
64'h800, // HaltAddress
64'h808 // ExceptionAddress
} ;

endpackage
4 changes: 3 additions & 1 deletion core/include/cv32a6_embedded_config_pkg.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -102,7 +102,9 @@ package cva6_config_pkg;
bit'(0), // XF8Vec
unsigned'(0), // NrRgprPorts
unsigned'(0), // NrWbPorts
bit'(0) // EnableAccelerator
bit'(0), // EnableAccelerator
64'h800, // HaltAddress
64'h808 // ExceptionAddress
} ;

endpackage
4 changes: 3 additions & 1 deletion core/include/cv32a6_ima_sv32_fpga_config_pkg.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -103,7 +103,9 @@ package cva6_config_pkg;
bit'(0), // XF8Vec
unsigned'(0), // NrRgprPorts
unsigned'(0), // NrWbPorts
bit'(0) // EnableAccelerator
bit'(0), // EnableAccelerator
64'h800, // HaltAddress
64'h808 // ExceptionAddress
} ;

endpackage
4 changes: 3 additions & 1 deletion core/include/cv32a6_imac_sv0_config_pkg.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -103,7 +103,9 @@ package cva6_config_pkg;
bit'(0), // XF8Vec
unsigned'(0), // NrRgprPorts
unsigned'(0), // NrWbPorts
bit'(0) // EnableAccelerator
bit'(0), // EnableAccelerator
64'h800, // HaltAddress
64'h808 // ExceptionAddress
} ;

endpackage
4 changes: 3 additions & 1 deletion core/include/cv32a6_imac_sv32_config_pkg.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -103,7 +103,9 @@ package cva6_config_pkg;
bit'(0), // XF8Vec
unsigned'(0), // NrRgprPorts
unsigned'(0), // NrWbPorts
bit'(0) // EnableAccelerator
bit'(0), // EnableAccelerator
64'h800, // HaltAddress
64'h808 // ExceptionAddress
} ;

endpackage
4 changes: 3 additions & 1 deletion core/include/cv32a6_imafc_sv32_config_pkg.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -103,7 +103,9 @@ package cva6_config_pkg;
bit'(0), // XF8Vec
unsigned'(0), // NrRgprPorts
unsigned'(0), // NrWbPorts
bit'(0) // EnableAccelerator
bit'(0), // EnableAccelerator
64'h800, // HaltAddress
64'h808 // ExceptionAddress
} ;

endpackage
4 changes: 3 additions & 1 deletion core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -103,7 +103,9 @@ package cva6_config_pkg;
bit'(0), // XF8Vec
unsigned'(0), // NrRgprPorts
unsigned'(0), // NrWbPorts
bit'(0) // EnableAccelerator
bit'(0), // EnableAccelerator
64'h800, // HaltAddress
64'h808 // ExceptionAddress
} ;

endpackage
4 changes: 3 additions & 1 deletion core/include/cv64a6_imafdc_sv39_config_pkg.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -103,7 +103,9 @@ package cva6_config_pkg;
bit'(0), // XF8Vec
unsigned'(0), // NrRgprPorts
unsigned'(0), // NrWbPorts
bit'(0) // EnableAccelerator
bit'(0), // EnableAccelerator
64'h800, // HaltAddress
64'h808 // ExceptionAddress // EnableAccelerator
} ;

endpackage
4 changes: 3 additions & 1 deletion core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -103,7 +103,9 @@ package cva6_config_pkg;
bit'(0), // XF8Vec
unsigned'(0), // NrRgprPorts
unsigned'(0), // NrWbPorts
bit'(0) // EnableAccelerator
bit'(0), // EnableAccelerator
64'h800, // HaltAddress
64'h808 // ExceptionAddress
} ;

endpackage
4 changes: 3 additions & 1 deletion core/include/cv64a6_imafdcv_sv39_config_pkg.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -103,7 +103,9 @@ package cva6_config_pkg;
bit'(0), // XF8Vec
unsigned'(0), // NrRgprPorts
unsigned'(0), // NrWbPorts
bit'(0) // EnableAccelerator
bit'(0), // EnableAccelerator
64'h800, // HaltAddress
64'h808 // ExceptionAddress
} ;

endpackage
6 changes: 6 additions & 0 deletions util/config_pkg_generator.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -103,6 +103,10 @@ def setup_parser_config_generator():
help="Cache type (WB or WT)")
parser.add_argument("--MmuPresent", type=int, default=None, choices=[0, 1],
help="Use an MMU ? 1 : enable, 0 : disable")
parser.add_argument("--HaltAddress", type=int, default=0x804,
help="Address which the core should jump in case of a debug request.")
parser.add_argument("--ExceptionAddress", type=int, default=0x808,
help="Address which the core should jump in case of an exception during debug mode.")
parser.add_argument("--RvfiTrace", type=int, default=None, choices=[0, 1],
help="Output an RVFI trace ? 1 : enable, 0 : disable")
return parser
Expand Down Expand Up @@ -156,6 +160,8 @@ def setup_parser_config_generator():
"MmuPresent": "CVA6ConfigMmuPresent",
# Ignored parameters
"ignored": "CVA6ConfigRvfiTrace",
"HaltAddress": "CVA6HaltAddress",
"ExceptionAddress": "CVA6ExceptionAddress",
}
MapParametersToArgs = {i:k for k, i in MapArgsToParameter.items()} #reverse map

Expand Down
Loading