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add RVFI CSRs tracing #184
add RVFI CSRs tracing #184
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rtl/cve2_cs_registers.sv
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@@ -12,6 +12,7 @@ | |||
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`include "prim_assert.sv" | |||
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import cve2_pkg::*; |
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can you move this after the module declaration?
`include "prim_assert.sv"
module cve2_cs_registers #(
parameter bit DbgTriggerEn = 0,
parameter int unsigned DbgHwBreakNum = 1,
parameter int unsigned MHPMCounterNum = 10,
parameter int unsigned MHPMCounterWidth = 40,
parameter bit PMPEnable = 0,
parameter int unsigned PMPGranularity = 0,
parameter int unsigned PMPNumRegions = 4,
parameter bit RV32E = 0,
parameter cve2_pkg::rv32m_e RV32M = cve2_pkg::RV32MFast,
parameter cve2_pkg::rv32b_e RV32B = cve2_pkg::RV32BNone
) (
// Clock and Reset
input logic clk_i,
input logic rst_ni,
....
input logic wfi_wait_i, // core waiting for interrupt
input logic div_wait_i // core waiting for divide
);
import cve2_pkg::*;
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Sure!
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Hi I am started to use this comit, I a unable to compile the design , It is throwing error in cve2_cs_register
where traces is added
Error found while trying to resolve cross-module reference.
token 'clknrst_if'. Originating module 'cve2_cs_registers' like this
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This has to be used with the new cv32e20-dv repo as this has the bind interfaces
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See #271 for additional discussion on this point.
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@MarioOpenHWGroup
I am not seeing anything in cv32e20 -dv , I am only seeing coming soon.
could help me out how to compile the design without error , I checked out this version.
I created allfile.txt with the help of cv32e20_manifest.flist and doing compile , do i need to add somthing to resolve the interface signals.
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my initial requirement is to fetch the data and write and read some date from memory,
how we need to provide the address map
I am new to this that why I am asking .
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Implementation of RVFI CSRs.
This supposes that the testbench binds a
rvfi_unified_csr_if
in thecs_registers.sv
module.