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    26 repositories

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      SystemVerilog
      •
      Apache License 2.0
      •21•0•0•0•Updated Oct 31, 2024Oct 31, 2024

    • iDMA

      Public
      A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
      SystemVerilog
      •
      Other
      •28•0•0•0•Updated Oct 22, 2024Oct 22, 2024

    • FABulous

      Public
      Fabric generator and CAD tools
      Python
      •
      Apache License 2.0
      •33•0•0•0•Updated Oct 5, 2024Oct 5, 2024

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •145•0•0•0•Updated Oct 4, 2024Oct 4, 2024

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      SystemVerilog
      •
      Other
      •265•0•0•0•Updated Oct 4, 2024Oct 4, 2024

    • riscv-dbg

      Public
      RISC-V Debug Support for our PULP RISC-V Cores
      SystemVerilog
      •
      Other
      •72•0•0•0•Updated Sep 24, 2024Sep 24, 2024

    • bender

      Public
      A dependency management tool for hardware projects.
      Rust
      •
      Apache License 2.0
      •37•0•0•0•Updated Aug 20, 2024Aug 20, 2024

    • hbm-utils

      Public
      HBM package and symbol generation scripts
      Python
      •0•0•0•0•Updated Aug 5, 2024Aug 5, 2024

    • SHARK-Turbine

      Public
      Unified compiler/runtime for interfacing with PyTorch Dynamo.
      Python
      •
      Apache License 2.0
      •48•0•0•0•Updated Jul 2, 2024Jul 2, 2024

    • mlir-llm-runner

      Public
      Python
      •
      Apache License 2.0
      •4•0•0•0•Updated Jun 28, 2024Jun 28, 2024

    • LLM-Viewer

      Public
      Analyze the inference of Large Language Models (LLMs). Analyze aspects like computation, storage, transmission, and hardware roofline model in a user-friendly interface.
      Python
      •
      MIT License
      •37•0•0•0•Updated Jun 26, 2024Jun 26, 2024

    • tinytrainer

      Public
      Using huggingface transformers library to create tiny language models
      Python
      •
      MIT License
      •1•0•0•0•Updated Jun 26, 2024Jun 26, 2024

    • llama2.c

      Public
      Inference Llama 2 in one file of pure C
      C
      •
      MIT License
      •2.1k•0•0•0•Updated Jun 25, 2024Jun 25, 2024

    • llama

      Public
      Inference code for LLaMA models
      Python
      •
      Other
      •9.6k•0•0•0•Updated Jun 25, 2024Jun 25, 2024

    • iree

      Public
      A retargetable MLIR-based machine learning compiler and runtime toolkit.
      C++
      •
      Apache License 2.0
      •609•0•0•0•Updated Jun 24, 2024Jun 24, 2024

    • common_verification

      Public
      SystemVerilog modules and classes commonly used for verification
      SystemVerilog
      •
      Other
      •12•0•0•0•Updated May 17, 2024May 17, 2024

    • cvfpu

      Public
      Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
      SystemVerilog
      •
      Other
      •115•0•0•1•Updated May 12, 2024May 12, 2024

    • register_interface

      Public
      Generic Register Interface (contains various adapters)
      SystemVerilog
      •
      Other
      •24•0•0•0•Updated Apr 13, 2024Apr 13, 2024

    • chat-builder

      Public
      Python
      •1•0•0•0•Updated Mar 4, 2024Mar 4, 2024

    • hero

      Public
      Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.
      SystemVerilog
      •
      Other
      •24•0•0•0•Updated Jan 18, 2024Jan 18, 2024

    • snitch_cluster

      Public
      An energy-efficient RISC-V floating-point compute cluster.
      SystemVerilog
      •
      Apache License 2.0
      •51•0•0•0•Updated Nov 24, 2023Nov 24, 2023

    • occamy

      Public
      A high-efficiency system-on-chip for floating-point compute workloads.
      Python
      •
      Apache License 2.0
      •11•0•0•0•Updated Nov 10, 2023Nov 10, 2023

    • snitch-public

      Public
      Lean but mean RISC-V system!
      SystemVerilog
      •
      Apache License 2.0
      •52•0•0•0•Updated Sep 18, 2023Sep 18, 2023

    • tech_cells_generic

      Public
      Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
      SystemVerilog
      •
      Other
      •30•0•0•0•Updated Aug 15, 2023Aug 15, 2023

    • KiPart

      Public
      Python package for generating multi-unit schematic symbols for KiCad from a CSV file.
      Python
      •
      MIT License
      •47•0•0•0•Updated Jul 26, 2023Jul 26, 2023

    • flexproxy

      Public
      flexlm proxy
      C
      •4•0•0•0•Updated Apr 14, 2016Apr 14, 2016