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1. common_verification common_verification Public

   Forked from pulp-platform/common_verification

   SystemVerilog modules and classes commonly used for verification

   SystemVerilog

2. tech_cells_generic tech_cells_generic Public

   Forked from pulp-platform/tech_cells_generic

   Technology dependent cells instantiated in the design for generic process (simulation, FPGA)

   SystemVerilog

3. common_cells common_cells Public

   Forked from pulp-platform/common_cells

   Common SystemVerilog components

   SystemVerilog

4. register_interface register_interface Public

   Forked from pulp-platform/register_interface

   Generic Register Interface (contains various adapters)

   SystemVerilog

5. axi axi Public

   Forked from pulp-platform/axi

   AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

   SystemVerilog 1

6. cvfpu cvfpu Public

   Forked from openhwgroup/cvfpu

   Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

   SystemVerilog