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Various enhancement #660

Merged
merged 6 commits into from
May 22, 2024
Merged

Various enhancement #660

merged 6 commits into from
May 22, 2024

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chungshien-chai
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@chungshien-chai chungshien-chai commented May 22, 2024 •
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Changes include:

  • Enhance existing set_clock_pin in auto-generated SDC to use net/naming in wrapped design (instead for orginal design)
  • Do not route BOOT_CLOCK to fabric if it is used only for clocking PLL. My new assumption now is xin_clk_l and xin_clk_r are hardwired and does not need fabric to control the routing.
  • For editor, has stricter checking on connection by seperating input and output ports. This prevent wrong direction connections.

Testing done:

  • Port this PR (together with Various enhancement  FOEDAG#1597) to latest NS Raptor
  • Run test/batch, test/batch_gen2. test/batch_gen3 and /up5bit_counter_dual_clock_bitstream, all GJCs project

@chungshien-chai chungshien-chai mentioned this pull request May 22, 2024
Merged
@alaindargelas alaindargelas merged commit 015c39c into main May 22, 2024
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@alaindargelas alaindargelas deleted the yosys-set-clock-pin branch May 22, 2024 16:32
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@alaindargelas alaindargelas Awaiting requested review from alaindargelas

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@chungshien-chai @alaindargelas