#10 load: update refcount of cap in Rd

project-starch · Sep 8, 2023 · b179428 · b179428
1 parent 8bdde73
commit b179428
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Showing 2 changed files with 13 additions and 7 deletions.
diff --git a/src/arch/riscvcapstone/isa/decoder.isa b/src/arch/riscvcapstone/isa/decoder.isa
@@ -1472,55 +1472,55 @@ decode QUADRANT default Unknown::unknown() {
                         Rs1_trv;
                         getMemLE(pkt, Mem_sb, traceData);
 
-                        Rd_sb = Mem_sb;
+                        Rd_trv.getRegVal().intVal() = Mem_sb;
                     }});
                 0x1: lh ({{ //ea_code
 
                     }}, {{ //comp_code
                         Rs1_trv;
                         getMemLE(pkt, Mem_sh, traceData);
 
-                        Rd_sh = Mem_sh;
+                        Rd_trv.getRegVal().intVal() = Mem_sh;
                     }});
                 0x2: lw ({{ //ea_code
 
                     }}, {{ //comp_code
                         Rs1_trv;
                         getMemLE(pkt, Mem_sw, traceData);
 
-                        Rd_sw = Mem_sw;
+                        Rd_trv.getRegVal().intVal() = Mem_sw;
                     }});
                 0x3: ld ({{ //ea_code
 
                     }}, {{ //comp_code
                         Rs1_trv;
                         getMemLE(pkt, Mem_sd, traceData);
 
-                        Rd_sd = Mem_sd;
+                        Rd_trv.getRegVal().intVal() = Mem_sd;
                     }});
                 0x4: lbu ({{ //ea_code
 
                     }}, {{ //comp_code
                         Rs1_trv;
                         getMemLE(pkt, Mem_ub, traceData);
 
-                        Rd_ub = Mem_ub;
+                        Rd_trv.getRegVal().intVal() = Mem_ub;
                     }});
                 0x5: lhu ({{ //ea_code
 
                     }}, {{ //comp_code
                         Rs1_trv;
                         getMemLE(pkt, Mem_uh, traceData);
 
-                        Rd_uh = Mem_uh;
+                        Rd_trv.getRegVal().intVal() = Mem_uh;
                     }});
                 0x6: lwu ({{ //ea_code
 
                     }}, {{ //comp_code
                         Rs1_trv;
                         getMemLE(pkt, Mem_uw, traceData);
 
-                        Rd_uw = Mem_uw;
+                        Rd_trv.getRegVal().intVal() = Mem_uw;
                     }});
             }
         }

diff --git a/src/arch/riscvcapstone/isa/formats/rnode.isa b/src/arch/riscvcapstone/isa/formats/rnode.isa
@@ -217,6 +217,12 @@ def template RNodeMemCompleteAcc {{
         %(op_decl)s;
         %(op_rd)s;
 
+        if(Rd.getTag()) {
+            Cap rd_cap = Rd.getRegVal().capVal();
+            NodeID node_id = rd_cap.nodeId();
+            dyn_inst->initiateNodeCommand(new NodeRcUpdate(node_id, -1));
+        }
+
         %(memacc_code)s;
         %(op_wb)s;
         return NoFault;