Add scripts to automatically run the tests and compile the results to…

… a csv - The tests are run on combinations of tag cache size and its memside connection Change-Id: I19a4f1782ffd42dc9712c715e94b2314e7ba42a7
project-starch · Jun 30, 2023 · f0630be · f0630be
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diff --git a/tests/capstone/o3/parse.py b/tests/capstone/o3/parse.py
@@ -0,0 +1,80 @@
+import os
+import sys
+import glob, csv
+import argparse
+
+parser = argparse.ArgumentParser()
+parser.add_argument('--input-folder', type=str, default='', help='input folder to parse files from')
+
+arg_delimiter_idx = sys.argv.index('--')
+
+args = parser.parse_args(sys.argv[1:arg_delimiter_idx])
+commands = sys.argv[arg_delimiter_idx + 1:]
+
+binary = commands[0]
+n = len(binary)
+
+os.chdir(args.input_folder)
+
+l2dict = {}
+memdict = {}
+
+for filename in glob.glob("*.txt"):
+    val = filename[n+1:]
+    coord = val.split('_')
+    tuple1 = (coord[0], coord[2].split('.')[0])
+
+    file1 = open(filename, 'r')
+    Lines = file1.readlines()
+
+    tcache_hits = "0"
+    tcache_misses = "0"
+    dcache_hits = "0"
+    dcache_misses = "0"
+    ncache_hits = "0"
+    ncache_misses = "0"
+    cycles = ""
+
+    for line in Lines:
+        xyz = line.split()
+        if "simTicks" in line:
+            if coord[1] == 'l2':
+                cycles = "%d, %.2f" % (int(xyz[1])/1000, round(int(xyz[1])/(1000*int(coord[0])),2))
+            else:
+                cycles = "%d, %.2f" % (int(xyz[1])/1000, round(int(xyz[1])/(1000*int(coord[0])),2))
+        elif "tcache.overallHits::total" in line:
+            tcache_hits = xyz[1]
+        elif "tcache.overallMisses::total" in line:
+            tcache_misses = xyz[1]
+        elif "dcache.overallHits::total" in line:
+            dcache_hits = xyz[1]
+        elif "dcache.overallMisses::total" in line:
+            dcache_misses = xyz[1]
+        elif "ncache.overallHits::total" in line:
+            ncache_hits = xyz[1]
+        elif "ncache.overallMisses::total" in line:
+            ncache_misses = xyz[1]
+
+    if coord[1] == 'l2':
+        l2dict[tuple1] = cycles + "\nTcache: "+tcache_hits+", "+tcache_misses + "\nDcache: "+dcache_hits+", "+dcache_misses + "\nNcache: "+ncache_hits+", "+ncache_misses
+    else:
+        memdict[tuple1] = cycles + "\nTcache: "+tcache_hits+", "+tcache_misses + "\nDcache: "+dcache_hits+", "+dcache_misses + "\nNcache: "+ncache_hits+", "+ncache_misses
+
+    file1.close()
+
+def create_csv_sheet(data, filename):
+    rows = sorted(set(key[0] for key in data.keys()), key=len)
+    columns = sorted(set(key[1] for key in data.keys()), key=len)
+
+    with open(filename, "w", newline="") as csvfile:
+        writer = csv.writer(csvfile, quoting=csv.QUOTE_ALL)
+
+        # Write the column headers
+        writer.writerow([""] + columns)
+
+        # Write the data rows
+        for row in rows:
+            writer.writerow([row] + [data.get((row, col), 0) for col in columns])
+
+create_csv_sheet(l2dict, 'l2.csv')
+create_csv_sheet(memdict, 'mem.csv')
diff --git a/tests/capstone/o3/perf_baseline.S b/tests/capstone/o3/perf_baseline.S
@@ -0,0 +1,82 @@
+//Baseline test corresponding to the mixed load scenario
+#include "asm_insn.h"
+
+.global _start
+_start:
+
+    INIT_RWX_CAP(a6)
+    li a1, 0x30000
+    li a2, 0x10000000
+    CAPBOUND(a6, a1, a2)
+    CAPPRINT(a6)
+
+    /**
+     * store some dummy value and check if it can
+     * can be correctly loaded by the loaded capabilities
+     */
+    li a7, 0x40000
+    SCC(a6, a7)
+    li a1, 0x42
+    sd a1, 0(a7)
+
+    li a3, xx
+    li a5, 0
+    li a7, 0x50000
+    SCC(a6, a7)
+
+_loop:
+    addi a3,a3,-1
+    //-------make cap-------//
+    CAPCREATE(a4)
+    li a2, CAP_TYPE_NONLIN
+    CAPTYPE(a4, a2)
+    li a1, NODE_ID_INVALID
+    ALLOC(a2, a1)
+    CAPNODE(a4, a2)
+    li a1, CAP_PERM_RO
+    CAPPERM(a4, a1)
+    li a1, 0x40000
+    li a2, 0x50000
+    CAPBOUND(a4, a1, a2)
+    //-------end make cap-------//
+    SDS(a6, a1)
+    addi a7, a7, 0x10
+    SCC(a6, a7)
+    bne a3, a5, _loop
+
+//workaround for assert(flags.isSet(STATIC_DATA|DYNAMIC_DATA))
+//for whatever reason that error is not coming anymore
+//.rept 1000
+//nop
+//.endr
+
+//-------warmup end-------//
+li t3, 1
+li t4, 0
+M5_EXIT
+
+_end_loop:
+    addi t4, t4, 1
+    li a3, xx
+    CAPPRINT(a3)
+    li a7, 0x50000
+    SCC(a6, a7)
+    li a4, 0x42
+
+_loop2:
+    addi a3,a3,-1
+    ld a2, 0(a7)
+    addi a7, a7, 0x10
+    //ld a1, 0(a2)
+    //fence    -------> delete this
+    //bne a1, a4, _test_fail
+    SCC(a6, a7)
+    bne a3, a5, _loop2
+
+    bne t4, t3, _end_loop
+    j exit
+
+_test_fail:
+    li a0, 0
+    li a7, 10
+    ecall
diff --git a/tests/capstone/o3/perf_baseline_ckpt.S b/tests/capstone/o3/perf_baseline_ckpt.S
@@ -0,0 +1,78 @@
+//Baseline test corresponding to the mixed load scenario
+#include "asm_insn.h"
+
+.global _start
+_start:
+
+    INIT_RWX_CAP(a6)
+    li a1, 0x30000
+    li a2, 0x10000000
+    CAPBOUND(a6, a1, a2)
+    CAPPRINT(a6)
+
+    /**
+     * store some dummy value and check if it can
+     * can be correctly loaded by the loaded capabilities
+     */
+    li a7, 0x40000
+    SCC(a6, a7)
+    li a1, 0x42
+    sd a1, 0(a7)
+
+    li a3, xx
+    li a5, 0
+    li a7, 0x50000
+    SCC(a6, a7)
+
+_loop:
+    addi a3,a3,-1
+    //-------make cap-------//
+    CAPCREATE(a4)
+    li a2, CAP_TYPE_NONLIN
+    CAPTYPE(a4, a2)
+    li a1, NODE_ID_INVALID
+    ALLOC(a2, a1)
+    CAPNODE(a4, a2)
+    li a1, CAP_PERM_RO
+    CAPPERM(a4, a1)
+    li a1, 0x40000
+    li a2, 0x50000
+    CAPBOUND(a4, a1, a2)
+    //-------end make cap-------//
+    SDS(a6, a1)
+    addi a7, a7, 0x10
+    SCC(a6, a7)
+    bne a3, a5, _loop
+
+//workaround for assert(flags.isSet(STATIC_DATA|DYNAMIC_DATA))
+//for whatever reason that error is not coming anymore
+//.rept 1000
+//nop
+//.endr
+
+//-------warmup end-------//
+M5_CHECKPOINT
+li t3, 1
+li t4, 0
+
+_end_loop:
+    addi t4, t4, 1
+    li a3, xx
+    CAPPRINT(a3)
+    li a7, 0x50000
+    li a4, 0x42
+
+_loop2:
+    addi a3,a3,-1
+    ld a2, 0(a7)
+    addi a7, a7, 0x10
+    ld a1, 0(a2)
+    bne a1, a4, _test_fail
+    bne a3, a5, _loop2
+    bne t4, t3, _end_loop
+    j exit
+
+_test_fail:
+    li a0, 0
+    li a7, 10
+    ecall
diff --git a/tests/capstone/o3/perf_baseline_random.S b/tests/capstone/o3/perf_baseline_random.S
@@ -0,0 +1,80 @@
+//Baseline test corresponding to the mixed load scenario
+#include "asm_insn.h"
+
+.global _start
+_start:
+
+    INIT_RWX_CAP(a6)
+    li a1, 0x30000
+    li a2, 0x10000000
+    CAPBOUND(a6, a1, a2)
+    CAPPRINT(a6)
+
+    /**
+     * store some dummy value and check if it can
+     * can be correctly loaded by the loaded capabilities
+     */
+    li a7, 0x40000
+    SCC(a6, a7)
+    li a1, 0x42
+    sd a1, 0(a7)
+
+    li a3, xx
+    li a5, 0
+    li a7, 0x50000
+    SCC(a6, a7)
+
+_loop:
+    addi a3,a3,-1
+    //-------make cap-------//
+    CAPCREATE(a4)
+    li a2, CAP_TYPE_NONLIN
+    CAPTYPE(a4, a2)
+    li a1, NODE_ID_INVALID
+    ALLOC(a2, a1)
+    CAPNODE(a4, a2)
+    li a1, CAP_PERM_RO
+    CAPPERM(a4, a1)
+    li a1, 0x40000
+    li a2, 0x50000
+    CAPBOUND(a4, a1, a2)
+    //-------end make cap-------//
+    SDS(a6, a1)
+    addi a7, a7, 0x10
+    SCC(a6, a7)
+    bne a3, a5, _loop
+
+//workaround for assert(flags.isSet(STATIC_DATA|DYNAMIC_DATA))
+//for whatever reason that error is not coming anymore
+//.rept 1000
+//nop
+//.endr
+
+//-------warmup end-------//
+li t3, 1
+li t4, 0
+mv t6, a7
+M5_EXIT
+
+_end_loop:
+    addi t4, t4, 1
+    li t5, 0x50000
+    li a3, xx
+    CAPPRINT(a3)
+    GETRAND(a7, t5, t6)
+    li a4, 0x42
+
+_loop2:
+    addi a3,a3,-1
+    ld a2, 0(a7)
+    GETRAND(a7, t5, t6)
+    ld a1, 0(a2)
+    bne a1, a4, _test_fail
+    bne a3, a5, _loop2
+    bne t4, t3, _end_loop
+    j exit
+
+_test_fail:
+    li a0, 0
+    li a7, 10
+    ecall