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Testing hyperram on FPGA #272

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Testing hyperram on FPGA #272

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aa5c168
fpga: Testing hyperram in block design
CyrilKoe Apr 24, 2024
5ee14d7
fpga: Testing hyperram in vanilla
CyrilKoe Apr 24, 2024
e4db6c6
fpga: Correct Xilinx IP verilog to follow the standard
CyrilKoe Jun 17, 2024
a3b96bd
fpga: Adding hyperram CDC constraints
CyrilKoe Jun 18, 2024
44fb3e4
fpga: Adding pads in vanilla
CyrilKoe Aug 14, 2024
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2 changes: 1 addition & 1 deletion carfield.mk
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Expand Up @@ -44,7 +44,7 @@ include $(CAR_ROOT)/bender-safed.mk
######################

CAR_NONFREE_REMOTE ?= [email protected]:carfield/carfield-nonfree.git
CAR_NONFREE_COMMIT ?= 59e53134
CAR_NONFREE_COMMIT ?= 7d227bc7

## @section Carfield platform nonfree components
## Clone the non-free verification IP for Carfield. Some components such as CI scripts and ASIC
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32 changes: 24 additions & 8 deletions target/xilinx/constraints/carfield_islands.tcl
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Expand Up @@ -41,13 +41,31 @@ handle_domain_clock_mux [get_cells -hier u_l2_clk_sel] 0 l2_domain_clk
# Carfield CDCs #
#################

# Safety Island
################
## Find the first parent cell of matching module from a list of object paths
## @param strs children objects paths
## @param ref_to_find the module type of the parent cell
proc find_parent_cell { strs ref_to_find } {
foreach str $strs {
set path ".";
foreach cell [split $str '/'] {
if {[get_cells -quiet $path] != ""} {
if { [get_property "ORIG_REF_NAME" [get_cell $path]] == $ref_to_find } {
return $path
}
if { [get_property "REF_NAME" [get_cell $path]] == $ref_to_find } {
return $path
}
}
set path $path/$cell;
}
}
return ""
}

proc handle_slv_cdc { slv_cdc_path } {
upvar SOC_TCK SOC_TCK
# Start from a known slv cdc_dst and get fanout to find the mst cdc_src
set mst_cdc_path [lindex [regexp -inline {.*i_cheshire_ext_slv_cdc_src|.*i_intcluster_slv_cdc} [lindex [filter [all_fanout -flat [get_pins $slv_cdc_path/*rptr*]] -filter {NAME =~ *gen_ext_slv_src_cdc* || NAME =~ *gen_pulp_cluster*}] 0]] 0]
set mst_cdc_path [find_parent_cell [all_fanout -flat [get_pins $slv_cdc_path/*rptr*]] "axi_cdc_src"]
if { $mst_cdc_path != "" } {
set_max_delay -datapath \
-from [get_pins $mst_cdc_path/i_cdc_fifo_gray_*/*reg*/C] \
Expand All @@ -66,7 +84,6 @@ proc handle_slv_cdc { slv_cdc_path } {
-to [get_pins $mst_cdc_path/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \
"$SOC_TCK"
}

}

handle_slv_cdc [get_cells -hier gen_periph.i_cdc_dst_peripherals]
Expand All @@ -76,12 +93,12 @@ handle_slv_cdc [get_cells -hier gen_safety_island.i_safety_island_wrap]/i_cdc_in
handle_slv_cdc [get_cells -hier gen_spatz_cluster.i_fp_cluster_wrapper]/i_spatz_cluster_cdc_dst
handle_slv_cdc [get_cells -hier gen_pulp_cluster.i_integer_cluster]/axi_slave_cdc_i
handle_slv_cdc [get_cells -hier gen_l2.i_reconfigurable_l2]/gen_cdc_fifos[0].i_dst_cdc
handle_slv_cdc [get_cells -hier i_hyperbus_wrap]/i_hyper_cdc_dst

proc handle_mst_cdc { mst_cdc_path } {
upvar SOC_TCK SOC_TCK
# Get the dst_cdc in cheshire
set slv_cdc_path [lindex [regexp -inline {.*i_cheshire_ext_mst_cdc_dst|.*i_intcluster_mst_cdc} [lindex [filter [all_fanout -flat [get_pins $mst_cdc_path/*wptr*]] -filter {NAME =~ *gen_ext_mst_dst_cdc* || NAME =~ *gen_pulp_cluster*}] 0]] 0]

# Start from a known mst cdc_src and get fanout to find the slv cdc_dst
set slv_cdc_path [find_parent_cell [all_fanout -flat [get_pins $mst_cdc_path/*rptr*]] "axi_cdc_dst"]
if { $slv_cdc_path != "" } {
# From Safety Island master
set_max_delay -datapath \
Expand All @@ -101,7 +118,6 @@ proc handle_mst_cdc { mst_cdc_path } {
-to [get_pins $mst_cdc_path/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \
"$SOC_TCK"
}

}

handle_mst_cdc [get_cells -hier gen_safety_island.i_safety_island_wrap]/i_cdc_out
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15 changes: 9 additions & 6 deletions target/xilinx/flavor_bd/.gitignore
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@@ -1,6 +1,9 @@
.Xil
carfield_*
scripts/add_sources.tcl*
scripts/add_includes.tcl
out/
probes.ltx
# Makefile
/out/
# Bender
/scripts/add_sources.tcl*
/scripts/add_includes.tcl
# Vivado
/.Xil
/carfield_*
/probes.ltx
6 changes: 6 additions & 0 deletions target/xilinx/flavor_bd/constraints/vcu128_ext_jtag.xdc
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@@ -1,3 +1,9 @@
# Copyright 2020 ETH Zurich and University of Bologna.
# Solderpad Hardware License, Version 0.51, see LICENSE for details.
# SPDX-License-Identifier: SHL-0.51
#
# Cyril Koenig <[email protected]>

set_property PACKAGE_PIN A23 [get_ports jtag_gnd_o] ;# A23 - C15 (FMCP_HSPC_LA10_N) - J1.04 - GND
set_property IOSTANDARD LVCMOS18 [get_ports jtag_gnd_o] ;

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64 changes: 37 additions & 27 deletions target/xilinx/flavor_bd/constraints/vcu128_hyperbus.xdc
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@@ -1,6 +1,15 @@
# Copyright 2020 ETH Zurich and University of Bologna.
# Solderpad Hardware License, Version 0.51, see LICENSE for details.
# SPDX-License-Identifier: SHL-0.51
#
# Cyril Koenig <[email protected]>

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets design_1_i/carfield_xilinx_ip_0/inst/i_carfield_xilinx/gen_hyper_phy[0].padinst_hyper_rwds0/iobuf_i/O]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {design_1_i/carfield_xilinx_ip_0/inst/i_carfield_xilinx/gen_hyper_phy[0].padinst_hyper_rwds0/iobuf_i/O}]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets gen_hyper_phy[0].padinst_hyper_rwds0/iobuf_i/O]

############
# Hyperbus #
############

#set_property PACKAGE_PIN A16 [get_ports "pad_hyper_csn[0]"] ;# (FMCP_HSPC_LA22_N) Bank 71 VCCO - VADJ - IO_L24N_T3U_N11_71
#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[0]"] ;# (FMCP_HSPC_LA22_N) Bank 71 VCCO - VADJ - IO_L24N_T3U_N11_71
Expand All @@ -10,35 +19,36 @@ set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets design_1_i/carfield_xilinx_ip
#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[6]"] ;# (FMCP_HSPC_LA20_P) Bank 71 VCCO - VADJ - IO_L22P_T3U_N6_DBC_AD0P_71
#set_property PACKAGE_PIN D20 [get_ports "pad_hyper_reset[0]"] ;# (FMCP_HSPC_LA25_P) Bank 71 VCCO - VADJ - IO_L18P_T2U_N10_AD2P_71
#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_reset[0]"] ;# (FMCP_HSPC_LA25_P) Bank 71 VCCO - VADJ - IO_L18P_T2U_N10_AD2P_71
set_property PACKAGE_PIN A24 [get_ports "pad_hyper_csn[1]"] ;# (FMCP_HSPC_LA13_N) Bank 72 VCCO - VADJ - IO_L24N_T3U_N11_72
set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[1]"] ;# (FMCP_HSPC_LA13_N) Bank 72 VCCO - VADJ - IO_L24N_T3U_N11_72
set_property PACKAGE_PIN A25 [get_ports "pad_hyper_csn[0]"] ;# (FMCP_HSPC_LA13_P) Bank 72 VCCO - VADJ - IO_L24P_T3U_N10_72
set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[0]"] ;# (FMCP_HSPC_LA13_P) Bank 72 VCCO - VADJ - IO_L24P_T3U_N10_72
set_property PACKAGE_PIN C23 [get_ports "pad_hyper_rwds[0]"] ;# (FMCP_HSPC_LA14_P) Bank 72 VCCO - VADJ - IO_L19P_T3L_N0_DBC_AD9P_72
set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_rwds[0]"] ;# (FMCP_HSPC_LA14_P) Bank 72 VCCO - VADJ - IO_L19P_T3L_N0_DBC_AD9P_72
set_property PACKAGE_PIN D26 [get_ports "pad_hyper_dq[2] "] ;# (FMCP_HSPC_LA09_N) Bank 72 VCCO - VADJ - IO_L17N_T2U_N9_AD10N_72
set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[2] "] ;# (FMCP_HSPC_LA09_N) Bank 72 VCCO - VADJ - IO_L17N_T2U_N9_AD10N_72
set_property PACKAGE_PIN A23 [get_ports pad_hyper_dq[3]] ;# (FMCP_HSPC_LA10_N)
set_property IOSTANDARD LVCMOS18 [get_ports pad_hyper_dq[3]] ;# (FMCP_HSPC_LA10_N)
set_property PACKAGE_PIN B23 [get_ports pad_hyper_dq[0]] ;# (FMCP_HSPC_LA10_P)
set_property IOSTANDARD LVCMOS18 [get_ports pad_hyper_dq[0]] ;# (FMCP_HSPC_LA10_P)
set_property PACKAGE_PIN E26 [get_ports "pad_hyper_dq[4]"] ;# (FMCP_HSPC_LA09_P) Bank 72 VCCO - VADJ - IO_L17P_T2U_N8_AD10P_72
set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[4]"] ;# (FMCP_HSPC_LA09_P) Bank 72 VCCO - VADJ - IO_L17P_T2U_N8_AD10P_72
set_property PACKAGE_PIN D22 [get_ports "pad_hyper_dq[7]"] ;# (FMCP_HSPC_LA06_N) Bank 72 VCCO - VADJ - IO_L15N_T2L_N5_AD11N_72
set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[7]"] ;# (FMCP_HSPC_LA06_N) Bank 72 VCCO - VADJ - IO_L15N_T2L_N5_AD11N_72
set_property PACKAGE_PIN E22 [get_ports "pad_hyper_dq[1]"] ;# (FMCP_HSPC_LA06_P) Bank 72 VCCO - VADJ - IO_L15P_T2L_N4_AD11P_72
set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[1]"] ;# (FMCP_HSPC_LA06_P) Bank 72 VCCO - VADJ - IO_L15P_T2L_N4_AD11P_72
set_property PACKAGE_PIN F25 [get_ports "pad_hyper_ckn[0]"] ;# (FMCP_HSPC_LA01_CC_N) Bank 72 VCCO - VADJ - IO_L14N_T2L_N3_GC_72
set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_ckn[0]"] ;# (FMCP_HSPC_LA01_CC_N) Bank 72 VCCO - VADJ - IO_L14N_T2L_N3_GC_72
set_property PACKAGE_PIN F26 [get_ports "pad_hyper_ck[0]"] ;# (FMCP_HSPC_LA01_CC_P) Bank 72 VCCO - VADJ - IO_L14P_T2L_N2_GC_72
set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_ck[0]"] ;# (FMCP_HSPC_LA01_CC_P) Bank 72 VCCO - VADJ - IO_L14P_T2L_N2_GC_72
set_property PACKAGE_PIN G27 [get_ports "pad_hyper_dq[5]"] ;# (FMCP_HSPC_LA05_N) Bank 72 VCCO - VADJ - IO_L9N_T1L_N5_AD12N_72
set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[5]"] ;# (FMCP_HSPC_LA05_N) Bank 72 VCCO - VADJ - IO_L9N_T1L_N5_AD12N_72
set_property PACKAGE_PIN H27 [get_ports "pad_hyper_dq[6]"] ;# (FMCP_HSPC_LA05_P) Bank 72 VCCO - VADJ - IO_L9P_T1L_N4_AD12P_72
set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[6]"] ;# (FMCP_HSPC_LA05_P) Bank 72 VCCO - VADJ - IO_L9P_T1L_N4_AD12P_72
set_property PACKAGE_PIN A24 [get_ports {pad_hyper_csn[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {pad_hyper_csn[1]}]
set_property PACKAGE_PIN A25 [get_ports {pad_hyper_csn[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {pad_hyper_csn[0]}]
set_property PACKAGE_PIN C23 [get_ports pad_hyper_rwds]
set_property IOSTANDARD LVCMOS18 [get_ports pad_hyper_rwds]
set_property PACKAGE_PIN D26 [get_ports {pad_hyper_dq[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {pad_hyper_dq[2]}]
set_property PACKAGE_PIN A23 [get_ports {pad_hyper_dq[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {pad_hyper_dq[3]}]
set_property PACKAGE_PIN B23 [get_ports {pad_hyper_dq[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {pad_hyper_dq[0]}]
set_property PACKAGE_PIN E26 [get_ports {pad_hyper_dq[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {pad_hyper_dq[4]}]
set_property PACKAGE_PIN D22 [get_ports {pad_hyper_dq[7]}]
set_property IOSTANDARD LVCMOS18 [get_ports {pad_hyper_dq[7]}]
set_property PACKAGE_PIN E22 [get_ports {pad_hyper_dq[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {pad_hyper_dq[1]}]
set_property PACKAGE_PIN F25 [get_ports pad_hyper_ckn]
set_property IOSTANDARD LVCMOS18 [get_ports pad_hyper_ckn]
set_property PACKAGE_PIN F26 [get_ports pad_hyper_ck]
set_property IOSTANDARD LVCMOS18 [get_ports pad_hyper_ck]
set_property PACKAGE_PIN G27 [get_ports {pad_hyper_dq[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {pad_hyper_dq[5]}]
set_property PACKAGE_PIN H27 [get_ports {pad_hyper_dq[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {pad_hyper_dq[6]}]
#set_property PACKAGE_PIN L23 [get_ports "pad_hyper_csn[1]"] ;# (FMCP_HSPC_LA02_P) Bank 72 VCCO - VADJ - IO_L4P_T0U_N6_DBC_AD7P_72
#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[1]"] ;# (FMCP_HSPC_LA02_P) Bank 72 VCCO - VADJ - IO_L4P_T0U_N6_DBC_AD7P_72
#set_property PACKAGE_PIN K23 [get_ports "pad_hyper_dq[5]"] ;# (FMCP_HSPC_LA16_N) Bank 72 VCCO - VADJ - IO_L3N_T0L_N5_AD15N_72
#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[5]"] ;# (FMCP_HSPC_LA16_N) Bank 72 VCCO - VADJ - IO_L3N_T0L_N5_AD15N_72
#set_property PACKAGE_PIN K24 [get_ports "pad_hyper_dq[4]"] ;# (FMCP_HSPC_LA16_P) Bank 72 VCCO - VADJ - IO_L3P_T0L_N4_AD15P_72
#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[4]"] ;# (FMCP_HSPC_LA16_P) Bank 72 VCCO - VADJ - IO_L3P_T0L_N4_AD15P_72

17 changes: 17 additions & 0 deletions target/xilinx/flavor_bd/scripts/carfield_bd_hyperbus.tcl
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@@ -0,0 +1,17 @@
# Copyright 2020 ETH Zurich and University of Bologna.
# Solderpad Hardware License, Version 0.51, see LICENSE for details.
# SPDX-License-Identifier: SHL-0.51
#
# Cyril Koenig <[email protected]>

set pad_hyper_ck [ create_bd_port -dir IO pad_hyper_ck ]
set pad_hyper_ckn [ create_bd_port -dir IO pad_hyper_ckn ]
set pad_hyper_csn [ create_bd_port -dir IO -from 1 -to 0 pad_hyper_csn ]
set pad_hyper_dq [ create_bd_port -dir IO -from 7 -to 0 pad_hyper_dq ]
set pad_hyper_rwds [ create_bd_port -dir IO pad_hyper_rwds ]

connect_bd_net [get_bd_ports pad_hyper_csn] [get_bd_pins carfield_xilinx_ip_0/pad_hyper_csn]
connect_bd_net [get_bd_ports pad_hyper_ck] [get_bd_pins carfield_xilinx_ip_0/pad_hyper_ck]
connect_bd_net [get_bd_ports pad_hyper_ckn] [get_bd_pins carfield_xilinx_ip_0/pad_hyper_ckn]
connect_bd_net [get_bd_ports pad_hyper_rwds] [get_bd_pins carfield_xilinx_ip_0/pad_hyper_rwds]
connect_bd_net [get_bd_ports pad_hyper_dq] [get_bd_pins carfield_xilinx_ip_0/pad_hyper_dq]
5 changes: 0 additions & 5 deletions target/xilinx/flavor_bd/scripts/carfield_bd_vcu128.tcl
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Expand Up @@ -463,11 +463,6 @@ proc create_root_design { parentCell } {
connect_bd_intf_net -intf_net xdma_0_pcie_mgt [get_bd_intf_ports pci_express_x1] [get_bd_intf_pins xdma_0/pcie_mgt]

# Create port connections
connect_bd_net -net Net [get_bd_pins carfield_xilinx_ip_0/pad_hyper_csn]
connect_bd_net -net Net1 [get_bd_pins carfield_xilinx_ip_0/pad_hyper_ck]
connect_bd_net -net Net2 [get_bd_pins carfield_xilinx_ip_0/pad_hyper_ckn]
connect_bd_net -net Net3 [get_bd_pins carfield_xilinx_ip_0/pad_hyper_rwds]
connect_bd_net -net Net4 [get_bd_pins carfield_xilinx_ip_0/pad_hyper_dq]
connect_bd_net -net axi_dma_0_mm2s_cntrl_reset_out_n [get_bd_pins axi_dma_0/mm2s_cntrl_reset_out_n] [get_bd_pins axi_ethernet_0/axi_txc_arstn]
connect_bd_net -net axi_dma_0_mm2s_introut [get_bd_pins axi_dma_0/mm2s_introut] [get_bd_pins concat_irq/In2]
connect_bd_net -net axi_dma_0_mm2s_prmry_reset_out_n [get_bd_pins axi_dma_0/mm2s_prmry_reset_out_n] [get_bd_pins axi_ethernet_0/axi_txd_arstn]
Expand Down
3 changes: 1 addition & 2 deletions target/xilinx/flavor_bd/scripts/run.tcl
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Expand Up @@ -34,9 +34,8 @@ if {[info exists ::env(GEN_EXT_JTAG)] && ($::env(GEN_EXT_JTAG)==1)} {

# Add the hyperbus pins to block design
if {![info exists ::env(GEN_NO_HYPERBUS)] || ($::env(GEN_NO_HYPERBUS)==0)} {
source scripts/carfield_bd_hyperbus.tcl
import_files -fileset constrs_1 -norecurse constraints/$::env(XILINX_BOARD)_hyperbus.xdc
} else {
delete_bd_objs [get_bd_ports pad_hyper*]
}

make_wrapper -files [get_files $project/$project.srcs/sources_1/bd/design_1/design_1.bd] -top
Expand Down
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