Add AW lock register to handle W FIFO push signal (#2461) #203
GitHub Actions / verible-verilog-format
failed
Oct 12, 2024 in 1s
reviewdog [verible-verilog-format] report
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Findings (4)
core/cache_subsystem/std_cache_subsystem.sv|193|
core/cache_subsystem/std_cache_subsystem.sv|204|
core/cache_subsystem/std_cache_subsystem.sv|206|
core/cache_subsystem/std_cache_subsystem.sv|210|
Filtered Findings (0)
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